w11 - vhd  0.75
W11 CPU core and support modules
sys_w11a_n3.vhd
Go to the documentation of this file.
1 -- $Id: sys_w11a_n3.vhd 888 2017-04-30 13:06:51Z mueller $
2 --
3 -- Copyright 2011-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 --
5 -- This program is free software; you may redistribute and/or modify it under
6 -- the terms of the GNU General Public License as published by the Free
7 -- Software Foundation, either version 2, or at your option any later version.
8 --
9 -- This program is distributed in the hope that it will be useful, but
10 -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11 -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 -- for complete details.
13 --
14 ------------------------------------------------------------------------------
15 -- Module Name: sys_w11a_n3 - syn
16 -- Description: w11a test design for nexys3
17 --
18 -- Dependencies: vlib/xlib/s6_cmt_sfs
19 -- vlib/genlib/clkdivce
20 -- bplib/bpgen/bp_rs232_2l4l_iob
21 -- bplib/fx2rlink/rlink_sp1c_fx2
22 -- w11a/pdp11_sys70
23 -- ibus/ibdr_maxisys
24 -- bplib/nxcramlib/nx_cram_memctl_as
25 -- bplib/fx2rlink/ioleds_sp1c_fx2
26 -- w11a/pdp11_hio70
27 -- bplib/bpgen/sn_humanio_rbus
28 -- vlib/rbus/rb_sres_or_2
29 --
30 -- Test bench: tb/tb_sys_w11a_n3
31 --
32 -- Target Devices: generic
33 -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.34
34 --
35 -- Synthesized (xst):
36 -- Date Rev ise Target flop lutl lutm slic t peri
37 -- 2017-03-30 888 14.7 131013 xc6slx16-2 2790 5352 177 1943 ok: +fx2dbg 85%
38 -- 2017-03-04 858 14.7 131013 xc6slx16-2 2717 5273 177 1885 ok: +deuna 82%
39 -- 2017-01-29 846 14.7 131013 xc6slx16-2 2680 5208 177 1860 ok: +int24 81%
40 -- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78%
41 -- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77%
42 -- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75%
43 -- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes
44 -- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67%
45 -- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67%
46 -- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65%
47 -- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 61%
48 -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon
49 -- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4
50 -- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11
51 -- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: 51%
52 -- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
53 -- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
54 -- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
55 --
56 -- Revision History:
57 -- Date Rev Version Comment
58 -- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
59 -- 2016-03-19 748 2.1.1 define rlink SYSID
60 -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
61 -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
62 -- 2015-04-24 668 1.8.3 added ibd_ibmon
63 -- 2015-04-11 666 1.8.2 rearrange XON handling
64 -- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
65 -- 2015-02-15 647 1.8 drop bram and minisys options
66 -- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address
67 -- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon
68 -- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT
69 -- 2014-08-15 583 1.6 rb_mreq addr now 16 bit
70 -- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
71 -- 2013-04-21 509 1.4 added fx2 (cuff) support
72 -- 2011-12-18 440 1.0.4 use rlink_sp1c
73 -- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
74 -- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
75 -- 2011-11-23 432 1.0.1 fixup PPCM handling
76 -- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
77 ------------------------------------------------------------------------------
78 --
79 -- w11a test design for nexys3
80 -- w11a + rlink + serport
81 --
82 -- Usage of Nexys 3 Switches, Buttons, LEDs:
83 --
84 -- SWI(7:6): select LED display mode
85 -- 0x w11 sys70 LED display (further controlled by SWI(3))
86 -- 10 FX2 debug: fx2 fifo states
87 -- 11 FX2 debug: fx2 fsm states
88 -- (5:4): select DSP
89 -- 00 abclkdiv & abclkdiv_f
90 -- 01 PC
91 -- 10 DISPREG
92 -- 11 DR emulation
93 -- (3): select LED display
94 -- 0 overall status
95 -- 1 DR emulation
96 -- (2) 0 -> int/ext RS242 port for rlink
97 -- 1 -> use USB interface for rlink
98 -- (1): 1 enable XON
99 -- (0): 0 -> main board RS232 port
100 -- 1 -> Pmod B/top RS232 port
101 --
102 -- LEDs if SWI(7) = 0 and SWI(3) = 1
103 -- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
104 --
105 -- LEDs if SWI(7) = 0 and SWI(3) = 0
106 -- (7) MEM_ACT_W
107 -- (6) MEM_ACT_R
108 -- (5) cmdbusy (all rlink access, mostly rdma)
109 -- (4:0) if cpugo=1 show cpu mode activity
110 -- (4) kernel mode, pri>0
111 -- (3) kernel mode, pri=0
112 -- (2) kernel mode, wait
113 -- (1) supervisor mode
114 -- (0) user mode
115 -- if cpugo=0 shows cpurust
116 -- (4) '1'
117 -- (3:0) cpurust code
118 --
119 -- LEDs if SWI(7) = 1
120 -- (7) fifo_ep4
121 -- (6) fifo_ep6
122 -- (5) fsm_rx
123 -- (4) fsm_tx
124 -- LEDs if SWI(7) = 1 and SWI(6) = 0
125 -- (3) flag_ep4_empty
126 -- (2) flag_ep4_almost
127 -- (1) flag_ep6_full
128 -- (0) flag_ep6_almost
129 -- LEDs if SWI(7) = 1 and SWI(6) = 1
130 -- (3) fsm_idle
131 -- (2) fsm_prep
132 -- (1) fsm_disp
133 -- (0) fsm_pipe
134 --
135 -- DP(3:0) shows IO activity
136 -- if SWI(2)=0 (serport)
137 -- (3): not SER_MONI.txok (shows tx back pressure)
138 -- (2): SER_MONI.txact (shows tx activity)
139 -- (1): not SER_MONI.rxok (shows rx back pressure)
140 -- (0): SER_MONI.rxact (shows rx activity)
141 -- if SWI(2)=1 (fx2-usb)
142 -- (3): RB_SRES.busy (shows rbus back pressure)
143 -- (2): RLB_TXBUSY (shows tx back pressure)
144 -- (1): RLB_TXENA (shows tx activity)
145 -- (0): RLB_RXVAL (shows rx activity)
146 --
147 
148 library ieee;
149 use ieee.std_logic_1164.all;
150 use ieee.numeric_std.all;
151 
152 use work.slvtypes.all;
153 use work.xlib.all;
154 use work.genlib.all;
155 use work.serportlib.all;
156 use work.rblib.all;
157 use work.rlinklib.all;
158 use work.fx2lib.all;
159 use work.fx2rlinklib.all;
160 use work.bpgenlib.all;
161 use work.bpgenrbuslib.all;
162 use work.nxcramlib.all;
163 use work.iblib.all;
164 use work.ibdlib.all;
165 use work.pdp11.all;
166 use work.sys_conf.all;
167 
168 -- ----------------------------------------------------------------------------
169 
170 entity sys_w11a_n3 is -- top level
171  -- implements nexys3_fusp_cuff_aif
172  port (
173  I_CLK100 : in slbit; -- 100 MHz clock
174  I_RXD : in slbit; -- receive data (board view)
175  O_TXD : out slbit; -- transmit data (board view)
176  I_SWI : in slv8; -- n3 switches
177  I_BTN : in slv5; -- n3 buttons
178  O_LED : out slv8; -- n3 leds
179  O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
180  O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
181  O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
182  O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
183  O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
184  O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
185  O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
186  O_MEM_CLK : out slbit; -- cram: clock
187  O_MEM_CRE : out slbit; -- cram: command register enable
188  I_MEM_WAIT : in slbit; -- cram: mem wait
189  O_MEM_ADDR : out slv23; -- cram: address lines
190  IO_MEM_DATA : inout slv16; -- cram: data lines
191  O_PPCM_CE_N : out slbit; -- ppcm: ...
192  O_PPCM_RST_N : out slbit; -- ppcm: ...
193  O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
194  I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
195  I_FUSP_RXD : in slbit; -- fusp: rs232 rx
196  O_FUSP_TXD : out slbit; -- fusp: rs232 tx
197  I_FX2_IFCLK : in slbit; -- fx2: interface clock
198  O_FX2_FIFO : out slv2; -- fx2: fifo address
199  I_FX2_FLAG : in slv4; -- fx2: fifo flags
200  O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
201  O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
202  O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
203  O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
204  IO_FX2_DATA : inout slv8 -- fx2: data lines
205  );
206 end sys_w11a_n3;
207 
208 architecture syn of sys_w11a_n3 is
209 
210  signal CLK : slbit := '0';
211 
212  signal RESET : slbit := '0';
213  signal CE_USEC : slbit := '0';
214  signal CE_MSEC : slbit := '0';
215 
216  signal RXD : slbit := '1';
217  signal TXD : slbit := '0';
218  signal RTS_N : slbit := '0';
219  signal CTS_N : slbit := '0';
220 
225 
226  signal RB_LAM : slv16 := (others=>'0');
227  signal RB_STAT : slv4 := (others=>'0');
228 
232 
233  signal GRESET : slbit := '0'; -- general reset (from rbus)
234  signal CRESET : slbit := '0'; -- cpu reset (from cp)
235  signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
236  signal ITIMER : slbit := '0';
237 
238  signal EI_PRI : slv3 := (others=>'0');
239  signal EI_VECT : slv9_2 := (others=>'0');
240  signal EI_ACKM : slbit := '0';
241 
244 
245  signal MEM_REQ : slbit := '0';
246  signal MEM_WE : slbit := '0';
247  signal MEM_BUSY : slbit := '0';
248  signal MEM_ACK_R : slbit := '0';
249  signal MEM_ACT_R : slbit := '0';
250  signal MEM_ACT_W : slbit := '0';
251  signal MEM_ADDR : slv20 := (others=>'0');
252  signal MEM_BE : slv4 := (others=>'0');
253  signal MEM_DI : slv32 := (others=>'0');
254  signal MEM_DO : slv32 := (others=>'0');
255 
256  signal MEM_ADDR_EXT : slv22 := (others=>'0');
257 
260 
261  signal DISPREG : slv16 := (others=>'0');
262  signal STATLEDS : slv8 := (others=>'0');
263  signal ABCLKDIV : slv16 := (others=>'0');
264 
265  signal LED70 : slv8 := (others=>'0');
266 
267  signal SWI : slv8 := (others=>'0');
268  signal BTN : slv5 := (others=>'0');
269  signal LED : slv8 := (others=>'0');
270  signal DSP_DAT : slv16 := (others=>'0');
271  signal DSP_DP : slv4 := (others=>'0');
272 
273  constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
274  constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
275 
276  constant sysid_proj : slv16 := x"0201"; -- w11a
277  constant sysid_board : slv8 := x"03"; -- nexys3
278  constant sysid_vers : slv8 := x"00";
279 
280 begin
281 
282  assert (sys_conf_clksys mod 1000000) = 0
283  report "assert sys_conf_clksys on MHz grid"
284  severity failure;
285 
286  GEN_CLKSYS : s6_cmt_sfs -- clock generator -------------------
287  generic map (
288  VCO_DIVIDE => sys_conf_clksys_vcodivide,
289  VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
290  OUT_DIVIDE => sys_conf_clksys_outdivide,
291  CLKIN_PERIOD => 10.0,
292  CLKIN_JITTER => 0.01,
293  STARTUP_WAIT => false,
294  GEN_TYPE => sys_conf_clksys_gentype)
295  port map (
296  CLKIN => I_CLK100,
297  CLKFX => CLK,
298  LOCKED => open
299  );
300 
301  CLKDIV : clkdivce -- usec/msec clock divider -----------
302  generic map (
303  CDUWIDTH => 7,
304  USECDIV => sys_conf_clksys_mhz,
305  MSECDIV => 1000)
306  port map (
307  CLK => CLK,
308  CE_USEC => CE_USEC,
309  CE_MSEC => CE_MSEC
310  );
311 
312  IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
313  port map (
314  CLK => CLK,
315  RESET => '0',
316  SEL => SWI(0),
317  RXD => RXD,
318  TXD => TXD,
319  CTS_N => CTS_N,
320  RTS_N => RTS_N,
321  I_RXD0 => I_RXD,
322  O_TXD0 => O_TXD,
323  I_RXD1 => I_FUSP_RXD,
324  O_TXD1 => O_FUSP_TXD,
325  I_CTS1_N => I_FUSP_CTS_N,
326  O_RTS1_N => O_FUSP_RTS_N
327  );
328 
329  RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
330  generic map (
331  BTOWIDTH => 7, -- 128 cycles access timeout
332  RTAWIDTH => 12,
333  SYSID => (others=>'0'),
334  IFAWIDTH => 5, -- 32 word input fifo
335  OFAWIDTH => 5, -- 32 word output fifo
336  PETOWIDTH => sys_conf_fx2_petowidth,
337  CCWIDTH => sys_conf_fx2_ccwidth,
338  ENAPIN_RLMON => sbcntl_sbf_rlmon,
339  ENAPIN_RBMON => sbcntl_sbf_rbmon,
340  CDWIDTH => 13,
341  CDINIT => sys_conf_ser2rri_cdinit,
342  RBMON_AWIDTH => sys_conf_rbmon_awidth,
343  RBMON_RBADDR => rbaddr_rbmon)
344  port map (
345  CLK => CLK,
346  CE_USEC => CE_USEC,
347  CE_MSEC => CE_MSEC,
348  CE_INT => CE_MSEC,
349  RESET => RESET,
350  ENAXON => SWI(1),
351  ENAFX2 => SWI(2),
352  RXSD => RXD,
353  TXSD => TXD,
354  CTS_N => CTS_N,
355  RTS_N => RTS_N,
356  RB_MREQ => RB_MREQ,
357  RB_SRES => RB_SRES,
358  RB_LAM => RB_LAM,
359  RB_STAT => RB_STAT,
360  RL_MONI => open,
361  RLB_MONI => RLB_MONI,
362  SER_MONI => SER_MONI,
363  FX2_MONI => FX2_MONI,
364  I_FX2_IFCLK => I_FX2_IFCLK,
365  O_FX2_FIFO => O_FX2_FIFO,
366  I_FX2_FLAG => I_FX2_FLAG,
367  O_FX2_SLRD_N => O_FX2_SLRD_N,
368  O_FX2_SLWR_N => O_FX2_SLWR_N,
369  O_FX2_SLOE_N => O_FX2_SLOE_N,
370  O_FX2_PKTEND_N => O_FX2_PKTEND_N,
371  IO_FX2_DATA => IO_FX2_DATA
372  );
373 
374  SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
375  port map (
376  CLK => CLK,
377  RESET => RESET,
378  RB_MREQ => RB_MREQ,
379  RB_SRES => RB_SRES_CPU,
380  RB_STAT => RB_STAT,
381  RB_LAM_CPU => RB_LAM(0),
382  GRESET => GRESET,
383  CRESET => CRESET,
384  BRESET => BRESET,
385  CP_STAT => CP_STAT,
386  EI_PRI => EI_PRI,
387  EI_VECT => EI_VECT,
388  EI_ACKM => EI_ACKM,
389  ITIMER => ITIMER,
390  IB_MREQ => IB_MREQ,
391  IB_SRES => IB_SRES_IBDR,
392  MEM_REQ => MEM_REQ,
393  MEM_WE => MEM_WE,
394  MEM_BUSY => MEM_BUSY,
395  MEM_ACK_R => MEM_ACK_R,
396  MEM_ADDR => MEM_ADDR,
397  MEM_BE => MEM_BE,
398  MEM_DI => MEM_DI,
399  MEM_DO => MEM_DO,
400  DM_STAT_DP => DM_STAT_DP
401  );
402 
403  IBDR_SYS : ibdr_maxisys -- IO system -------------------------
404  port map (
405  CLK => CLK,
406  CE_USEC => CE_USEC,
407  CE_MSEC => CE_MSEC,
408  RESET => GRESET,
409  BRESET => BRESET,
410  ITIMER => ITIMER,
411  CPUSUSP => CP_STAT.cpususp,
412  RB_LAM => RB_LAM(15 downto 1),
413  IB_MREQ => IB_MREQ,
414  IB_SRES => IB_SRES_IBDR,
415  EI_ACKM => EI_ACKM,
416  EI_PRI => EI_PRI,
417  EI_VECT => EI_VECT,
418  DISPREG => DISPREG
419  );
420 
421  MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
422 
423  CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
424  generic map (
425  READ0DELAY => sys_conf_memctl_read0delay,
426  READ1DELAY => sys_conf_memctl_read1delay,
427  WRITEDELAY => sys_conf_memctl_writedelay)
428  port map (
429  CLK => CLK,
430  RESET => GRESET,
431  REQ => MEM_REQ,
432  WE => MEM_WE,
433  BUSY => MEM_BUSY,
434  ACK_R => MEM_ACK_R,
435  ACK_W => open,
436  ACT_R => MEM_ACT_R,
437  ACT_W => MEM_ACT_W,
438  ADDR => MEM_ADDR_EXT,
439  BE => MEM_BE,
440  DI => MEM_DI,
441  DO => MEM_DO,
442  O_MEM_CE_N => O_MEM_CE_N,
443  O_MEM_BE_N => O_MEM_BE_N,
444  O_MEM_WE_N => O_MEM_WE_N,
445  O_MEM_OE_N => O_MEM_OE_N,
446  O_MEM_ADV_N => O_MEM_ADV_N,
447  O_MEM_CLK => O_MEM_CLK,
448  O_MEM_CRE => O_MEM_CRE,
449  I_MEM_WAIT => I_MEM_WAIT,
450  O_MEM_ADDR => O_MEM_ADDR,
451  IO_MEM_DATA => IO_MEM_DATA
452  );
453 
454  O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
455  O_PPCM_RST_N <= '1'; --
456 
457  LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
458  port map (
459  CLK => CLK,
460  CE_USEC => CE_USEC,
461  RESET => GRESET,
462  ENAFX2 => SWI(2),
463  RB_SRES => RB_SRES,
464  RLB_MONI => RLB_MONI,
465  SER_MONI => SER_MONI,
466  IOLEDS => DSP_DP
467  );
468 
469  ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
470 
471  HIO70 : pdp11_hio70 -- hio from sys70 --------------------
472  generic map (
473  LWIDTH => LED'length,
474  DCWIDTH => 2)
475  port map (
476  SEL_LED => SWI(3),
477  SEL_DSP => SWI(5 downto 4),
478  MEM_ACT_R => MEM_ACT_R,
479  MEM_ACT_W => MEM_ACT_W,
480  CP_STAT => CP_STAT,
481  DM_STAT_DP => DM_STAT_DP,
482  ABCLKDIV => ABCLKDIV,
483  DISPREG => DISPREG,
484  LED => LED70,
485  DSP_DAT => DSP_DAT
486  );
487 
488  proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------
489  variable iled : slv8 := (others=>'0');
490  begin
491 
492  iled := (others=>'0');
493  if SWI(7) = '0' then
494  iled := LED70;
495  else
496  iled(7) := FX2_MONI.fifo_ep4;
497  iled(6) := FX2_MONI.fifo_ep6;
498  iled(5) := FX2_MONI.fsm_rx;
499  iled(4) := FX2_MONI.fsm_tx;
500  if SWI(6) = '0' then
501  iled(3) := FX2_MONI.flag_ep4_empty;
502  iled(2) := FX2_MONI.flag_ep4_almost;
503  iled(1) := FX2_MONI.flag_ep6_full;
504  iled(0) := FX2_MONI.flag_ep6_almost;
505  else
506  iled(3) := FX2_MONI.fsm_idle;
507  iled(2) := FX2_MONI.fsm_prep;
508  iled(1) := FX2_MONI.fsm_disp;
509  iled(0) := FX2_MONI.fsm_pipe;
510  end if;
511  end if;
512  LED <= iled;
513 
514  end process proc_fx2leds;
515 
516  HIO : sn_humanio_rbus -- hio manager -----------------------
517  generic map (
518  BWIDTH => 5,
519  DEBOUNCE => sys_conf_hio_debounce,
520  RB_ADDR => rbaddr_hio)
521  port map (
522  CLK => CLK,
523  RESET => RESET,
524  CE_MSEC => CE_MSEC,
525  RB_MREQ => RB_MREQ,
526  RB_SRES => RB_SRES_HIO,
527  SWI => SWI,
528  BTN => BTN,
529  LED => LED,
530  DSP_DAT => DSP_DAT,
531  DSP_DP => DSP_DP,
532  I_SWI => I_SWI,
533  I_BTN => I_BTN,
534  O_LED => O_LED,
535  O_ANO_N => O_ANO_N,
536  O_SEG_N => O_SEG_N
537  );
538 
539  RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
540  port map (
541  RB_SRES_1 => RB_SRES_CPU,
542  RB_SRES_2 => RB_SRES_HIO,
543  RB_SRES_OR => RB_SRES
544  );
545 
546 end syn;
out O_TXDslbit
positive := 1 sys_conf_clksys_vcodivide
rb_sres_type
Definition: rblib.vhd:57
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:65
slv4 :=( others => '0') DSP_DP
out O_FX2_FIFOslv2
rlink_sp1c_fx2 rlinkrlink
Definition: xlib.vhd:41
dm_stat_dp_type := dm_stat_dp_init DM_STAT_DP
slbit := '0' CRESET
slbit := '0' CE_USEC
out O_MEM_CREslbit
Definition: iblib.vhd:38
positive := cram_read0delay(sys_conf_clksys_mhz ) sys_conf_memctl_read0delay
Definition: sys_conf.vhd:53
inout IO_MEM_DATAslv16
rlb_moni_type :=( '0', '0', '0', '0') rlb_moni_init
Definition: rlinklib.vhd:119
ib_sres_type
Definition: iblib.vhd:59
fx2ctl_moni_type := fx2ctl_moni_init FX2_MONI
out O_MEM_CLKslbit
cp_stat_type := cp_stat_init CP_STAT
inout IO_FX2_DATAslv8
out O_FUSP_RTS_Nslbit
slbit fsm_idle
Definition: fx2lib.vhd:58
in I_FX2_FLAGslv4
slv16 := x"0201" sysid_proj
slv8 :=( others => '0') LED70
fx2ctl_moni_type :=( '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0') fx2ctl_moni_init
Definition: fx2lib.vhd:67
rb_mreq_type
Definition: rblib.vhd:43
rb_mreq_type :=( '0', '0', '0', '0',( others => '0'),( others => '0')) rb_mreq_init
Definition: rblib.vhd:52
slbit := '0' EI_ACKM
dm_stat_dp_type :=(( others => '0'), psw_init, '0',( others => '0'), '0',( others => '0'), '0',( others => '0'), '0',( others => '0'), '0',( others => '0'), '0',( others => '0'),( others => '0'), '0', '0') dm_stat_dp_init
Definition: pdp11.vhd:645
positive := 5 sys_conf_fx2_ccwidth
Definition: sys_conf.vhd:51
out O_MEM_BE_Nslv2
slbit fsm_pipe
Definition: fx2lib.vhd:61
slv4 :=( others => '0') RB_STAT
positive := cram_writedelay(sys_conf_clksys_mhz ) sys_conf_memctl_writedelay
Definition: sys_conf.vhd:57
positive := 10 sys_conf_fx2_petowidth
Definition: sys_conf.vhd:49
slbit := '0' MEM_ACT_R
slv8 :=( others => '0') STATLEDS
out O_SEG_Nslv8
slbit flag_ep6_almost
Definition: fx2lib.vhd:52
ib_mreq_type
Definition: iblib.vhd:40
slbit := '0' ITIMER
rb_sres_type := rb_sres_init RB_SRES_HIO
slbit := '0' MEM_WE
slbit := '0' RESET
slbit flag_ep4_almost
Definition: fx2lib.vhd:50
cp_stat_type :=( '0', '0', '0', '0', '0', '0', '0', '0',( others => '0'), '0', '0') cp_stat_init
Definition: pdp11.vhd:583
rlb_moni_type := rlb_moni_init RLB_MONI
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') ABCLKDIV
pdp11_sys70 sys70sys70
std_logic_vector( 21 downto 0) slv22
Definition: slvtypes.vhd:64
slv16 abclkdiv
Definition: serportlib.vhd:179
integer :=(( 100000000/ sys_conf_clksys_vcodivide)* sys_conf_clksys_vcomultiply)/ sys_conf_clksys_outdivide sys_conf_clksys
out O_FX2_SLRD_Nslbit
slbit := '0' MEM_REQ
out O_PPCM_RST_Nslbit
slbit := '0' GRESET
integer := sys_conf_clksys/ 1000000 sys_conf_clksys_mhz
in I_FX2_IFCLKslbit
out O_FX2_SLOE_Nslbit
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:57
in I_BTNslv5
out O_MEM_ADDRslv23
slbit := '0' TXD
slbit := '0' MEM_ACT_W
sn_humanio_rbus hiohio
out O_FX2_PKTEND_Nslbit
integer := 13 sbcntl_sbf_rbmon
Definition: rblib.vhd:181
Definition: pdp11.vhd:109
slbit := '0' MEM_BUSY
out O_PPCM_CE_Nslbit
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:68
serport_moni_type := serport_moni_init SER_MONI
ib_sres_type :=( '0', '0',( others => '0')) ib_sres_init
Definition: iblib.vhd:65
in I_MEM_WAITslbit
slv8 := x"03" sysid_board
cp_stat_type
Definition: pdp11.vhd:569
slv16 :=( others => '0') DISPREG
out O_MEM_ADV_Nslbit
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:43
out O_MEM_WE_Nslbit
positive := 8 sys_conf_clksys_vcomultiply
slv3 :=( others => '0') EI_PRI
slbit := '0' CLK
slbit := '0' RTS_N
_library_ ieeeieee
in I_SWIslv8
slv8 :=( others => '0') SWI
slbit fsm_prep
Definition: fx2lib.vhd:59
positive := 10 sys_conf_clksys_outdivide
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:45
slbit fifo_ep4
Definition: fx2lib.vhd:46
slbit fsm_disp
Definition: fx2lib.vhd:60
serport_moni_type :=( '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0'), '0', '0') serport_moni_init
Definition: serportlib.vhd:185
slv22 :=( others => '0') MEM_ADDR_EXT
integer :=( sys_conf_clksys/ sys_conf_ser2rri_defbaud)- 1 sys_conf_ser2rri_cdinit
Definition: sys_conf.vhd:54
out O_FUSP_TXDslbit
rb_mreq_type := rb_mreq_init RB_MREQ
slv4 :=( others => '0') MEM_BE
rb_sres_type := rb_sres_init RB_SRES_CPU
slbit flag_ep4_empty
Definition: fx2lib.vhd:49
slv8 :=( others => '0') LED
slv32 :=( others => '0') MEM_DI
in I_RXDslbit
rb_sres_type :=( '0', '0', '0',( others => '0')) rb_sres_init
Definition: rblib.vhd:64
string := "MMCM" sys_conf_clksys_gentype
in I_CLK100slbit
ib_sres_type := ib_sres_init IB_SRES_IBDR
slv16 := x"fef0" rbaddr_hio
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:44
in I_FUSP_CTS_Nslbit
ib_mreq_type :=( '0', '0', '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0')) ib_mreq_init
Definition: iblib.vhd:53
slv5 :=( others => '0') BTN
boolean := true sys_conf_hio_debounce
Definition: sys_conf.vhd:42
out O_MEM_CE_Nslbit
integer := 15 sbcntl_sbf_rlmon
Definition: rlinklib.vhd:124
out O_ANO_Nslv4
ib_mreq_type := ib_mreq_init IB_MREQ
Definition: rblib.vhd:41
slv9_2 :=( others => '0') EI_VECT
out O_LEDslv8
integer := 0 sys_conf_rbmon_awidth
Definition: sys_conf.vhd:60
slbit := '1' RXD
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:49
in I_FUSP_RXDslbit
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:62
positive := cram_read1delay(sys_conf_clksys_mhz ) sys_conf_memctl_read1delay
Definition: sys_conf.vhd:55
out O_FX2_SLWR_Nslbit
out O_MEM_OE_Nslbit
slv32 :=( others => '0') MEM_DO
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:74
slbit fsm_tx
Definition: fx2lib.vhd:63
dm_stat_dp_type
Definition: pdp11.vhd:625
fx2ctl_moni_type
Definition: fx2lib.vhd:45
slv3 abclkdiv_f
Definition: serportlib.vhd:180
slbit := '0' MEM_ACK_R
slv16 := x"ffe8" rbaddr_rbmon
slv16 :=( others => '0') RB_LAM
slv20 :=( others => '0') MEM_ADDR
std_logic slbit
Definition: slvtypes.vhd:39
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:46
slbit fsm_rx
Definition: fx2lib.vhd:62
slbit := '0' BRESET
slbit := '0' CE_MSEC
slbit fifo_ep6
Definition: fx2lib.vhd:47
slbit flag_ep6_full
Definition: fx2lib.vhd:51
slv16 :=( others => '0') DSP_DAT
slbit := '0' CTS_N
slv8 := x"00" sysid_vers