w11 - vhd  0.73
W11 CPU core and support modules
sys_w11a_n3.vhd
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1 -- $Id: sys_w11a_n3.vhd 748 2016-03-20 15:18:50Z mueller $
2 --
3 -- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 --
5 -- This program is free software; you may redistribute and/or modify it under
6 -- the terms of the GNU General Public License as published by the Free
7 -- Software Foundation, either version 2, or at your option any later version.
8 --
9 -- This program is distributed in the hope that it will be useful, but
10 -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11 -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 -- for complete details.
13 --
14 ------------------------------------------------------------------------------
15 -- Module Name: sys_w11a_n3 - syn
16 -- Description: w11a test design for nexys3
17 --
18 -- Dependencies: vlib/xlib/s6_cmt_sfs
19 -- vlib/genlib/clkdivce
20 -- bplib/bpgen/bp_rs232_2l4l_iob
21 -- bplib/fx2rlink/rlink_sp1c_fx2
22 -- w11a/pdp11_sys70
23 -- ibus/ibdr_maxisys
24 -- bplib/nxcramlib/nx_cram_memctl_as
25 -- bplib/fx2rlink/ioleds_sp1c_fx2
26 -- w11a/pdp11_hio70
27 -- bplib/bpgen/sn_humanio_rbus
28 -- vlib/rbus/rb_sres_or_2
29 --
30 -- Test bench: tb/tb_sys_w11a_n3
31 --
32 -- Target Devices: generic
33 -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
34 --
35 -- Synthesized (xst):
36 -- Date Rev ise Target flop lutl lutm slic t peri
37 -- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78%
38 -- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77%
39 -- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75%
40 -- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes
41 -- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67%
42 -- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67%
43 -- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65%
44 -- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 61%
45 -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon
46 -- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4
47 -- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11
48 -- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: 51%
49 -- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
50 -- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
51 -- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
52 --
53 -- Revision History:
54 -- Date Rev Version Comment
55 -- 2016-03-19 748 2.1.1 define rlink SYSID
56 -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
57 -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
58 -- 2015-04-24 668 1.8.3 added ibd_ibmon
59 -- 2015-04-11 666 1.8.2 rearrange XON handling
60 -- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
61 -- 2015-02-15 647 1.8 drop bram and minisys options
62 -- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address
63 -- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon
64 -- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT
65 -- 2014-08-15 583 1.6 rb_mreq addr now 16 bit
66 -- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
67 -- 2013-04-21 509 1.4 added fx2 (cuff) support
68 -- 2011-12-18 440 1.0.4 use rlink_sp1c
69 -- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
70 -- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
71 -- 2011-11-23 432 1.0.1 fixup PPCM handling
72 -- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
73 ------------------------------------------------------------------------------
74 --
75 -- w11a test design for nexys3
76 -- w11a + rlink + serport
77 --
78 -- Usage of Nexys 3 Switches, Buttons, LEDs:
79 --
80 -- SWI(7:6): no function (only connected to sn_humanio_rbus)
81 -- (5:4): select DSP
82 -- 00 abclkdiv & abclkdiv_f
83 -- 01 PC
84 -- 10 DISPREG
85 -- 11 DR emulation
86 -- (3): select LED display
87 -- 0 overall status
88 -- 1 DR emulation
89 -- (2) 0 -> int/ext RS242 port for rlink
90 -- 1 -> use USB interface for rlink
91 -- (1): 1 enable XON
92 -- (0): 0 -> main board RS232 port
93 -- 1 -> Pmod B/top RS232 port
94 --
95 -- LEDs if SWI(3) = 1
96 -- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
97 --
98 -- LEDs if SWI(3) = 0
99 -- (7) MEM_ACT_W
100 -- (6) MEM_ACT_R
101 -- (5) cmdbusy (all rlink access, mostly rdma)
102 -- (4:0) if cpugo=1 show cpu mode activity
103 -- (4) kernel mode, pri>0
104 -- (3) kernel mode, pri=0
105 -- (2) kernel mode, wait
106 -- (1) supervisor mode
107 -- (0) user mode
108 -- if cpugo=0 shows cpurust
109 -- (4) '1'
110 -- (3:0) cpurust code
111 --
112 -- DP(3:0) shows IO activity
113 -- if SWI(2)=0 (serport)
114 -- (3): not SER_MONI.txok (shows tx back preasure)
115 -- (2): SER_MONI.txact (shows tx activity)
116 -- (1): not SER_MONI.rxok (shows rx back preasure)
117 -- (0): SER_MONI.rxact (shows rx activity)
118 -- if SWI(2)=1 (fx2-usb)
119 -- (3): RB_SRES.busy (shows rbus back preasure)
120 -- (2): RLB_TXBUSY (shows tx back preasure)
121 -- (1): RLB_TXENA (shows tx activity)
122 -- (0): RLB_RXVAL (shows rx activity)
123 --
124 
125 library ieee;
126 use ieee.std_logic_1164.all;
127 use ieee.numeric_std.all;
128 
129 use work.slvtypes.all;
130 use work.xlib.all;
131 use work.genlib.all;
132 use work.serportlib.all;
133 use work.rblib.all;
134 use work.rlinklib.all;
135 use work.fx2lib.all;
136 use work.fx2rlinklib.all;
137 use work.bpgenlib.all;
138 use work.bpgenrbuslib.all;
139 use work.nxcramlib.all;
140 use work.iblib.all;
141 use work.ibdlib.all;
142 use work.pdp11.all;
143 use work.sys_conf.all;
144 
145 -- ----------------------------------------------------------------------------
146 
147 entity sys_w11a_n3 is -- top level
148  -- implements nexys3_fusp_cuff_aif
149  port (
150  I_CLK100 : in slbit; -- 100 MHz clock
151  I_RXD : in slbit; -- receive data (board view)
152  O_TXD : out slbit; -- transmit data (board view)
153  I_SWI : in slv8; -- n3 switches
154  I_BTN : in slv5; -- n3 buttons
155  O_LED : out slv8; -- n3 leds
156  O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
157  O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
158  O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
159  O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
160  O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
161  O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
162  O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
163  O_MEM_CLK : out slbit; -- cram: clock
164  O_MEM_CRE : out slbit; -- cram: command register enable
165  I_MEM_WAIT : in slbit; -- cram: mem wait
166  O_MEM_ADDR : out slv23; -- cram: address lines
167  IO_MEM_DATA : inout slv16; -- cram: data lines
168  O_PPCM_CE_N : out slbit; -- ppcm: ...
169  O_PPCM_RST_N : out slbit; -- ppcm: ...
170  O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
171  I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
172  I_FUSP_RXD : in slbit; -- fusp: rs232 rx
173  O_FUSP_TXD : out slbit; -- fusp: rs232 tx
174  I_FX2_IFCLK : in slbit; -- fx2: interface clock
175  O_FX2_FIFO : out slv2; -- fx2: fifo address
176  I_FX2_FLAG : in slv4; -- fx2: fifo flags
177  O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
178  O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
179  O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
180  O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
181  IO_FX2_DATA : inout slv8 -- fx2: data lines
182  );
183 end sys_w11a_n3;
184 
185 architecture syn of sys_w11a_n3 is
186 
187  signal CLK : slbit := '0';
188 
189  signal RESET : slbit := '0';
190  signal CE_USEC : slbit := '0';
191  signal CE_MSEC : slbit := '0';
192 
193  signal RXD : slbit := '1';
194  signal TXD : slbit := '0';
195  signal RTS_N : slbit := '0';
196  signal CTS_N : slbit := '0';
197 
202 
203  signal RB_LAM : slv16 := (others=>'0');
204  signal RB_STAT : slv4 := (others=>'0');
205 
209 
210  signal GRESET : slbit := '0'; -- general reset (from rbus)
211  signal CRESET : slbit := '0'; -- cpu reset (from cp)
212  signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
213  signal ITIMER : slbit := '0';
214 
215  signal EI_PRI : slv3 := (others=>'0');
216  signal EI_VECT : slv9_2 := (others=>'0');
217  signal EI_ACKM : slbit := '0';
218 
221 
222  signal MEM_REQ : slbit := '0';
223  signal MEM_WE : slbit := '0';
224  signal MEM_BUSY : slbit := '0';
225  signal MEM_ACK_R : slbit := '0';
226  signal MEM_ACT_R : slbit := '0';
227  signal MEM_ACT_W : slbit := '0';
228  signal MEM_ADDR : slv20 := (others=>'0');
229  signal MEM_BE : slv4 := (others=>'0');
230  signal MEM_DI : slv32 := (others=>'0');
231  signal MEM_DO : slv32 := (others=>'0');
232 
233  signal MEM_ADDR_EXT : slv22 := (others=>'0');
234 
237 
238  signal DISPREG : slv16 := (others=>'0');
239  signal STATLEDS : slv8 := (others=>'0');
240  signal ABCLKDIV : slv16 := (others=>'0');
241 
242  signal SWI : slv8 := (others=>'0');
243  signal BTN : slv5 := (others=>'0');
244  signal LED : slv8 := (others=>'0');
245  signal DSP_DAT : slv16 := (others=>'0');
246  signal DSP_DP : slv4 := (others=>'0');
247 
248  constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
249  constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
250 
251  constant sysid_proj : slv16 := x"0201"; -- w11a
252  constant sysid_board : slv8 := x"03"; -- nexys3
253  constant sysid_vers : slv8 := x"00";
254 
255 begin
256 
257  assert (sys_conf_clksys mod 1000000) = 0
258  report "assert sys_conf_clksys on MHz grid"
259  severity failure;
260 
261  GEN_CLKSYS : s6_cmt_sfs -- clock generator -------------------
262  generic map (
263  VCO_DIVIDE => sys_conf_clksys_vcodivide,
264  VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
265  OUT_DIVIDE => sys_conf_clksys_outdivide,
266  CLKIN_PERIOD => 10.0,
267  CLKIN_JITTER => 0.01,
268  STARTUP_WAIT => false,
269  GEN_TYPE => sys_conf_clksys_gentype)
270  port map (
271  CLKIN => I_CLK100,
272  CLKFX => CLK,
273  LOCKED => open
274  );
275 
276  CLKDIV : clkdivce -- usec/msec clock divider -----------
277  generic map (
278  CDUWIDTH => 7,
279  USECDIV => sys_conf_clksys_mhz,
280  MSECDIV => 1000)
281  port map (
282  CLK => CLK,
283  CE_USEC => CE_USEC,
284  CE_MSEC => CE_MSEC
285  );
286 
287  IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
288  port map (
289  CLK => CLK,
290  RESET => '0',
291  SEL => SWI(0),
292  RXD => RXD,
293  TXD => TXD,
294  CTS_N => CTS_N,
295  RTS_N => RTS_N,
296  I_RXD0 => I_RXD,
297  O_TXD0 => O_TXD,
298  I_RXD1 => I_FUSP_RXD,
299  O_TXD1 => O_FUSP_TXD,
300  I_CTS1_N => I_FUSP_CTS_N,
301  O_RTS1_N => O_FUSP_RTS_N
302  );
303 
304  RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
305  generic map (
306  BTOWIDTH => 7, -- 128 cycles access timeout
307  RTAWIDTH => 12,
308  SYSID => (others=>'0'),
309  IFAWIDTH => 5, -- 32 word input fifo
310  OFAWIDTH => 5, -- 32 word output fifo
311  PETOWIDTH => sys_conf_fx2_petowidth,
312  CCWIDTH => sys_conf_fx2_ccwidth,
313  ENAPIN_RLMON => sbcntl_sbf_rlmon,
314  ENAPIN_RBMON => sbcntl_sbf_rbmon,
315  CDWIDTH => 13,
316  CDINIT => sys_conf_ser2rri_cdinit,
317  RBMON_AWIDTH => sys_conf_rbmon_awidth,
318  RBMON_RBADDR => rbaddr_rbmon)
319  port map (
320  CLK => CLK,
321  CE_USEC => CE_USEC,
322  CE_MSEC => CE_MSEC,
323  CE_INT => CE_MSEC,
324  RESET => RESET,
325  ENAXON => SWI(1),
326  ENAFX2 => SWI(2),
327  RXSD => RXD,
328  TXSD => TXD,
329  CTS_N => CTS_N,
330  RTS_N => RTS_N,
331  RB_MREQ => RB_MREQ,
332  RB_SRES => RB_SRES,
333  RB_LAM => RB_LAM,
334  RB_STAT => RB_STAT,
335  RL_MONI => open,
336  RLB_MONI => RLB_MONI,
337  SER_MONI => SER_MONI,
338  FX2_MONI => FX2_MONI,
339  I_FX2_IFCLK => I_FX2_IFCLK,
340  O_FX2_FIFO => O_FX2_FIFO,
341  I_FX2_FLAG => I_FX2_FLAG,
342  O_FX2_SLRD_N => O_FX2_SLRD_N,
343  O_FX2_SLWR_N => O_FX2_SLWR_N,
344  O_FX2_SLOE_N => O_FX2_SLOE_N,
345  O_FX2_PKTEND_N => O_FX2_PKTEND_N,
346  IO_FX2_DATA => IO_FX2_DATA
347  );
348 
349  SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
350  port map (
351  CLK => CLK,
352  RESET => RESET,
353  RB_MREQ => RB_MREQ,
354  RB_SRES => RB_SRES_CPU,
355  RB_STAT => RB_STAT,
356  RB_LAM_CPU => RB_LAM(0),
357  GRESET => GRESET,
358  CRESET => CRESET,
359  BRESET => BRESET,
360  CP_STAT => CP_STAT,
361  EI_PRI => EI_PRI,
362  EI_VECT => EI_VECT,
363  EI_ACKM => EI_ACKM,
364  ITIMER => ITIMER,
365  IB_MREQ => IB_MREQ,
366  IB_SRES => IB_SRES_IBDR,
367  MEM_REQ => MEM_REQ,
368  MEM_WE => MEM_WE,
369  MEM_BUSY => MEM_BUSY,
370  MEM_ACK_R => MEM_ACK_R,
371  MEM_ADDR => MEM_ADDR,
372  MEM_BE => MEM_BE,
373  MEM_DI => MEM_DI,
374  MEM_DO => MEM_DO,
375  DM_STAT_DP => DM_STAT_DP
376  );
377 
378  IBDR_SYS : ibdr_maxisys -- IO system -------------------------
379  port map (
380  CLK => CLK,
381  CE_USEC => CE_USEC,
382  CE_MSEC => CE_MSEC,
383  RESET => GRESET,
384  BRESET => BRESET,
385  ITIMER => ITIMER,
386  CPUSUSP => CP_STAT.cpususp,
387  RB_LAM => RB_LAM(15 downto 1),
388  IB_MREQ => IB_MREQ,
389  IB_SRES => IB_SRES_IBDR,
390  EI_ACKM => EI_ACKM,
391  EI_PRI => EI_PRI,
392  EI_VECT => EI_VECT,
393  DISPREG => DISPREG
394  );
395 
396  MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
397 
398  SRAM_CTL: nx_cram_memctl_as -- memory controller -----------------
399  generic map (
400  READ0DELAY => sys_conf_memctl_read0delay,
401  READ1DELAY => sys_conf_memctl_read1delay,
402  WRITEDELAY => sys_conf_memctl_writedelay)
403  port map (
404  CLK => CLK,
405  RESET => GRESET,
406  REQ => MEM_REQ,
407  WE => MEM_WE,
408  BUSY => MEM_BUSY,
409  ACK_R => MEM_ACK_R,
410  ACK_W => open,
411  ACT_R => MEM_ACT_R,
412  ACT_W => MEM_ACT_W,
413  ADDR => MEM_ADDR_EXT,
414  BE => MEM_BE,
415  DI => MEM_DI,
416  DO => MEM_DO,
417  O_MEM_CE_N => O_MEM_CE_N,
418  O_MEM_BE_N => O_MEM_BE_N,
419  O_MEM_WE_N => O_MEM_WE_N,
420  O_MEM_OE_N => O_MEM_OE_N,
421  O_MEM_ADV_N => O_MEM_ADV_N,
422  O_MEM_CLK => O_MEM_CLK,
423  O_MEM_CRE => O_MEM_CRE,
424  I_MEM_WAIT => I_MEM_WAIT,
425  O_MEM_ADDR => O_MEM_ADDR,
426  IO_MEM_DATA => IO_MEM_DATA
427  );
428 
429  O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
430  O_PPCM_RST_N <= '1'; --
431 
432  LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
433  port map (
434  CLK => CLK,
435  CE_USEC => CE_USEC,
436  RESET => GRESET,
437  ENAFX2 => SWI(2),
438  RB_SRES => RB_SRES,
439  RLB_MONI => RLB_MONI,
440  SER_MONI => SER_MONI,
441  IOLEDS => DSP_DP
442  );
443 
444  ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
445 
446  HIO70 : pdp11_hio70 -- hio from sys70 --------------------
447  generic map (
448  LWIDTH => LED'length,
449  DCWIDTH => 2)
450  port map (
451  SEL_LED => SWI(3),
452  SEL_DSP => SWI(5 downto 4),
453  MEM_ACT_R => MEM_ACT_R,
454  MEM_ACT_W => MEM_ACT_W,
455  CP_STAT => CP_STAT,
456  DM_STAT_DP => DM_STAT_DP,
457  ABCLKDIV => ABCLKDIV,
458  DISPREG => DISPREG,
459  LED => LED,
460  DSP_DAT => DSP_DAT
461  );
462 
463  HIO : sn_humanio_rbus -- hio manager -----------------------
464  generic map (
465  BWIDTH => 5,
466  DEBOUNCE => sys_conf_hio_debounce,
467  RB_ADDR => rbaddr_hio)
468  port map (
469  CLK => CLK,
470  RESET => RESET,
471  CE_MSEC => CE_MSEC,
472  RB_MREQ => RB_MREQ,
473  RB_SRES => RB_SRES_HIO,
474  SWI => SWI,
475  BTN => BTN,
476  LED => LED,
477  DSP_DAT => DSP_DAT,
478  DSP_DP => DSP_DP,
479  I_SWI => I_SWI,
480  I_BTN => I_BTN,
481  O_LED => O_LED,
482  O_ANO_N => O_ANO_N,
483  O_SEG_N => O_SEG_N
484  );
485 
486  RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
487  port map (
488  RB_SRES_1 => RB_SRES_CPU,
489  RB_SRES_2 => RB_SRES_HIO,
490  RB_SRES_OR => RB_SRES
491  );
492 
493 end syn;
out O_TXDslbit
positive := 1 sys_conf_clksys_vcodivide
Definition: sys_conf.vhd:35
rb_sres_type
Definition: rblib.vhd:57
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:64
slv4 :=( others => '0') DSP_DP
out O_FX2_FIFOslv2
rlink_sp1c_fx2 rlinkrlink
Definition: xlib.vhd:41
dm_stat_dp_type := dm_stat_dp_init DM_STAT_DP
slbit := '0' CRESET
slbit := '0' CE_USEC
out O_MEM_CREslbit
Definition: iblib.vhd:37
positive := sys_conf_memctl_read0delay sys_conf_memctl_read1delay
Definition: sys_conf.vhd:70
positive := 3 sys_conf_memctl_read0delay
Definition: sys_conf.vhd:69
inout IO_MEM_DATAslv16
rlb_moni_type :=( '0', '0', '0', '0') rlb_moni_init
Definition: rlinklib.vhd:119
ib_sres_type
Definition: iblib.vhd:58
fx2ctl_moni_type := fx2ctl_moni_init FX2_MONI
out O_MEM_CLKslbit
cp_stat_type := cp_stat_init CP_STAT
inout IO_FX2_DATAslv8
out O_FUSP_RTS_Nslbit
in I_FX2_FLAGslv4
slv16 := x"0201" sysid_proj
rb_mreq_type
Definition: rblib.vhd:43
rb_mreq_type :=( '0', '0', '0', '0',( others => '0'),( others => '0')) rb_mreq_init
Definition: rblib.vhd:52
slbit := '0' EI_ACKM
dm_stat_dp_type :=(( others => '0'), psw_init, '0',( others => '0'), '0',( others => '0'), '0',( others => '0'), '0',( others => '0'), '0',( others => '0'), '0',( others => '0'),( others => '0'), '0', '0') dm_stat_dp_init
Definition: pdp11.vhd:636
positive := 5 sys_conf_fx2_ccwidth
Definition: sys_conf.vhd:51
out O_MEM_BE_Nslv2
slv4 :=( others => '0') RB_STAT
positive := 10 sys_conf_fx2_petowidth
Definition: sys_conf.vhd:49
slbit := '0' MEM_ACT_R
slv8 :=( others => '0') STATLEDS
out O_SEG_Nslv8
ib_mreq_type
Definition: iblib.vhd:39
slbit := '0' ITIMER
rb_sres_type := rb_sres_init RB_SRES_HIO
slbit := '0' MEM_WE
slbit := '0' RESET
cp_stat_type :=( '0', '0', '0', '0', '0', '0', '0', '0',( others => '0'), '0', '0') cp_stat_init
Definition: pdp11.vhd:581
rlb_moni_type := rlb_moni_init RLB_MONI
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') ABCLKDIV
pdp11_sys70 sys70sys70
std_logic_vector( 21 downto 0) slv22
Definition: slvtypes.vhd:63
slv16 abclkdiv
Definition: serportlib.vhd:179
integer :=(( 100000000/ sys_conf_clksys_vcodivide)* sys_conf_clksys_vcomultiply)/ sys_conf_clksys_outdivide sys_conf_clksys
Definition: sys_conf.vhd:49
out O_FX2_SLRD_Nslbit
slbit := '0' MEM_REQ
out O_PPCM_RST_Nslbit
slbit := '0' GRESET
integer := sys_conf_clksys/ 1000000 sys_conf_clksys_mhz
Definition: sys_conf.vhd:52
in I_FX2_IFCLKslbit
out O_FX2_SLOE_Nslbit
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:56
in I_BTNslv5
out O_MEM_ADDRslv23
slbit := '0' TXD
slbit := '0' MEM_ACT_W
sn_humanio_rbus hiohio
out O_FX2_PKTEND_Nslbit
integer := 13 sbcntl_sbf_rbmon
Definition: rblib.vhd:181
Definition: pdp11.vhd:107
slbit := '0' MEM_BUSY
out O_PPCM_CE_Nslbit
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:67
serport_moni_type := serport_moni_init SER_MONI
ib_sres_type :=( '0', '0',( others => '0')) ib_sres_init
Definition: iblib.vhd:64
in I_MEM_WAITslbit
slv8 := x"03" sysid_board
cp_stat_type
Definition: pdp11.vhd:567
slv16 :=( others => '0') DISPREG
out O_MEM_ADV_Nslbit
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:42
out O_MEM_WE_Nslbit
positive := 12 sys_conf_clksys_vcomultiply
Definition: sys_conf.vhd:36
slv3 :=( others => '0') EI_PRI
slbit := '0' CLK
slbit := '0' RTS_N
_library_ ieeeieee
in I_SWIslv8
slv8 :=( others => '0') SWI
positive := 10 sys_conf_clksys_outdivide
Definition: sys_conf.vhd:37
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:44
serport_moni_type :=( '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0'), '0', '0') serport_moni_init
Definition: serportlib.vhd:185
slv22 :=( others => '0') MEM_ADDR_EXT
integer :=( sys_conf_clksys/ sys_conf_ser2rri_defbaud)- 1 sys_conf_ser2rri_cdinit
Definition: sys_conf.vhd:54
out O_FUSP_TXDslbit
rb_mreq_type := rb_mreq_init RB_MREQ
slv4 :=( others => '0') MEM_BE
rb_sres_type := rb_sres_init RB_SRES_CPU
slv8 :=( others => '0') LED
slv32 :=( others => '0') MEM_DI
in I_RXDslbit
rb_sres_type :=( '0', '0', '0',( others => '0')) rb_sres_init
Definition: rblib.vhd:64
string := "MMCM" sys_conf_clksys_gentype
Definition: sys_conf.vhd:38
in I_CLK100slbit
ib_sres_type := ib_sres_init IB_SRES_IBDR
slv16 := x"fef0" rbaddr_hio
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:43
in I_FUSP_CTS_Nslbit
ib_mreq_type :=( '0', '0', '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0')) ib_mreq_init
Definition: iblib.vhd:52
slv5 :=( others => '0') BTN
boolean := true sys_conf_hio_debounce
Definition: sys_conf.vhd:42
out O_MEM_CE_Nslbit
integer := 15 sbcntl_sbf_rlmon
Definition: rlinklib.vhd:124
out O_ANO_Nslv4
ib_mreq_type := ib_mreq_init IB_MREQ
Definition: rblib.vhd:41
slv9_2 :=( others => '0') EI_VECT
out O_LEDslv8
integer := 0 sys_conf_rbmon_awidth
Definition: sys_conf.vhd:58
slbit := '1' RXD
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:48
in I_FUSP_RXDslbit
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:61
fx2ctl_moni_type :=( '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0') fx2ctl_moni_init
Definition: fx2lib.vhd:59
out O_FX2_SLWR_Nslbit
out O_MEM_OE_Nslbit
slv32 :=( others => '0') MEM_DO
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:73
dm_stat_dp_type
Definition: pdp11.vhd:616
fx2ctl_moni_type
Definition: fx2lib.vhd:44
slv3 abclkdiv_f
Definition: serportlib.vhd:180
slbit := '0' MEM_ACK_R
slv16 := x"ffe8" rbaddr_rbmon
slv16 :=( others => '0') RB_LAM
slv20 :=( others => '0') MEM_ADDR
std_logic slbit
Definition: slvtypes.vhd:38
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:45
slbit := '0' BRESET
slbit := '0' CE_MSEC
slv16 :=( others => '0') DSP_DAT
slbit := '0' CTS_N
positive := 4 sys_conf_memctl_writedelay
Definition: sys_conf.vhd:71
slv8 := x"00" sysid_vers