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sys_w11a_n3.vhd
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1 -- $Id: sys_w11a_n3.vhd 734 2016-02-20 22:43:20Z mueller $
2 --
3 -- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4 --
5 -- This program is free software; you may redistribute and/or modify it under
6 -- the terms of the GNU General Public License as published by the Free
7 -- Software Foundation, either version 2, or at your option any later version.
8 --
9 -- This program is distributed in the hope that it will be useful, but
10 -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11 -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 -- for complete details.
13 --
14 ------------------------------------------------------------------------------
15 -- Module Name: sys_w11a_n3 - syn
16 -- Description: w11a test design for nexys3
17 --
18 -- Dependencies: vlib/xlib/s6_cmt_sfs
19 -- vlib/genlib/clkdivce
20 -- bplib/bpgen/bp_rs232_2l4l_iob
21 -- bplib/fx2rlink/rlink_sp1c_fx2
22 -- w11a/pdp11_sys70
23 -- ibus/ibdr_maxisys
24 -- bplib/nxcramlib/nx_cram_memctl_as
25 -- bplib/fx2rlink/ioleds_sp1c_fx2
26 -- w11a/pdp11_hio70
27 -- bplib/bpgen/sn_humanio_rbus
28 -- vlib/rbus/rb_sres_or_2
29 --
30 -- Test bench: tb/tb_sys_w11a_n3
31 --
32 -- Target Devices: generic
33 -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
34 --
35 -- Synthesized (xst):
36 -- Date Rev ise Target flop lutl lutm slic t peri
37 -- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78%
38 -- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77%
39 -- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75%
40 -- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes
41 -- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67%
42 -- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67%
43 -- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65%
44 -- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 61%
45 -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon
46 -- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4
47 -- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11
48 -- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: 51%
49 -- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
50 -- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
51 -- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
52 --
53 -- Revision History:
54 -- Date Rev Version Comment
55 -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
56 -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
57 -- 2015-04-24 668 1.8.3 added ibd_ibmon
58 -- 2015-04-11 666 1.8.2 rearrange XON handling
59 -- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
60 -- 2015-02-15 647 1.8 drop bram and minisys options
61 -- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address
62 -- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon
63 -- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT
64 -- 2014-08-15 583 1.6 rb_mreq addr now 16 bit
65 -- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
66 -- 2013-04-21 509 1.4 added fx2 (cuff) support
67 -- 2011-12-18 440 1.0.4 use rlink_sp1c
68 -- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
69 -- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
70 -- 2011-11-23 432 1.0.1 fixup PPCM handling
71 -- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
72 ------------------------------------------------------------------------------
73 --
74 -- w11a test design for nexys3
75 -- w11a + rlink + serport
76 --
77 -- Usage of Nexys 3 Switches, Buttons, LEDs:
78 --
79 -- SWI(7:6): no function (only connected to sn_humanio_rbus)
80 -- (5:4): select DSP
81 -- 00 abclkdiv & abclkdiv_f
82 -- 01 PC
83 -- 10 DISPREG
84 -- 11 DR emulation
85 -- (3): select LED display
86 -- 0 overall status
87 -- 1 DR emulation
88 -- (2) 0 -> int/ext RS242 port for rlink
89 -- 1 -> use USB interface for rlink
90 -- (1): 1 enable XON
91 -- (0): 0 -> main board RS232 port
92 -- 1 -> Pmod B/top RS232 port
93 --
94 -- LEDs if SWI(3) = 1
95 -- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
96 --
97 -- LEDs if SWI(3) = 0
98 -- (7) MEM_ACT_W
99 -- (6) MEM_ACT_R
100 -- (5) cmdbusy (all rlink access, mostly rdma)
101 -- (4:0) if cpugo=1 show cpu mode activity
102 -- (4) kernel mode, pri>0
103 -- (3) kernel mode, pri=0
104 -- (2) kernel mode, wait
105 -- (1) supervisor mode
106 -- (0) user mode
107 -- if cpugo=0 shows cpurust
108 -- (4) '1'
109 -- (3:0) cpurust code
110 --
111 -- DP(3:0) shows IO activity
112 -- if SWI(2)=0 (serport)
113 -- (3): not SER_MONI.txok (shows tx back preasure)
114 -- (2): SER_MONI.txact (shows tx activity)
115 -- (1): not SER_MONI.rxok (shows rx back preasure)
116 -- (0): SER_MONI.rxact (shows rx activity)
117 -- if SWI(2)=1 (fx2-usb)
118 -- (3): RB_SRES.busy (shows rbus back preasure)
119 -- (2): RLB_TXBUSY (shows tx back preasure)
120 -- (1): RLB_TXENA (shows tx activity)
121 -- (0): RLB_RXVAL (shows rx activity)
122 --
123 
124 library ieee;
125 use ieee.std_logic_1164.all;
126 use ieee.numeric_std.all;
127 
128 use work.slvtypes.all;
129 use work.xlib.all;
130 use work.genlib.all;
131 use work.serportlib.all;
132 use work.rblib.all;
133 use work.rlinklib.all;
134 use work.fx2lib.all;
135 use work.fx2rlinklib.all;
136 use work.bpgenlib.all;
137 use work.bpgenrbuslib.all;
138 use work.nxcramlib.all;
139 use work.iblib.all;
140 use work.ibdlib.all;
141 use work.pdp11.all;
142 use work.sys_conf.all;
143 
144 -- ----------------------------------------------------------------------------
145 
146 entity sys_w11a_n3 is -- top level
147  -- implements nexys3_fusp_cuff_aif
148  port (
149  I_CLK100 : in slbit; -- 100 MHz clock
150  I_RXD : in slbit; -- receive data (board view)
151  O_TXD : out slbit; -- transmit data (board view)
152  I_SWI : in slv8; -- n3 switches
153  I_BTN : in slv5; -- n3 buttons
154  O_LED : out slv8; -- n3 leds
155  O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
156  O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
157  O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
158  O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
159  O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
160  O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
161  O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
162  O_MEM_CLK : out slbit; -- cram: clock
163  O_MEM_CRE : out slbit; -- cram: command register enable
164  I_MEM_WAIT : in slbit; -- cram: mem wait
165  O_MEM_ADDR : out slv23; -- cram: address lines
166  IO_MEM_DATA : inout slv16; -- cram: data lines
167  O_PPCM_CE_N : out slbit; -- ppcm: ...
168  O_PPCM_RST_N : out slbit; -- ppcm: ...
169  O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
170  I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
171  I_FUSP_RXD : in slbit; -- fusp: rs232 rx
172  O_FUSP_TXD : out slbit; -- fusp: rs232 tx
173  I_FX2_IFCLK : in slbit; -- fx2: interface clock
174  O_FX2_FIFO : out slv2; -- fx2: fifo address
175  I_FX2_FLAG : in slv4; -- fx2: fifo flags
176  O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
177  O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
178  O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
179  O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
180  IO_FX2_DATA : inout slv8 -- fx2: data lines
181  );
182 end sys_w11a_n3;
183 
184 architecture syn of sys_w11a_n3 is
185 
186  signal CLK : slbit := '0';
187 
188  signal RESET : slbit := '0';
189  signal CE_USEC : slbit := '0';
190  signal CE_MSEC : slbit := '0';
191 
192  signal RXD : slbit := '1';
193  signal TXD : slbit := '0';
194  signal RTS_N : slbit := '0';
195  signal CTS_N : slbit := '0';
196 
197  signal RB_MREQ : rb_mreq_type := rb_mreq_init;
198  signal RB_SRES : rb_sres_type := rb_sres_init;
199  signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
200  signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
201 
202  signal RB_LAM : slv16 := (others=>'0');
203  signal RB_STAT : slv4 := (others=>'0');
204 
205  signal RLB_MONI : rlb_moni_type := rlb_moni_init;
206  signal SER_MONI : serport_moni_type := serport_moni_init;
207  signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
208 
209  signal GRESET : slbit := '0'; -- general reset (from rbus)
210  signal CRESET : slbit := '0'; -- cpu reset (from cp)
211  signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
212  signal ITIMER : slbit := '0';
213 
214  signal EI_PRI : slv3 := (others=>'0');
215  signal EI_VECT : slv9_2 := (others=>'0');
216  signal EI_ACKM : slbit := '0';
217 
218  signal CP_STAT : cp_stat_type := cp_stat_init;
219  signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
220 
221  signal MEM_REQ : slbit := '0';
222  signal MEM_WE : slbit := '0';
223  signal MEM_BUSY : slbit := '0';
224  signal MEM_ACK_R : slbit := '0';
225  signal MEM_ACT_R : slbit := '0';
226  signal MEM_ACT_W : slbit := '0';
227  signal MEM_ADDR : slv20 := (others=>'0');
228  signal MEM_BE : slv4 := (others=>'0');
229  signal MEM_DI : slv32 := (others=>'0');
230  signal MEM_DO : slv32 := (others=>'0');
231 
232  signal MEM_ADDR_EXT : slv22 := (others=>'0');
233 
234  signal IB_MREQ : ib_mreq_type := ib_mreq_init;
235  signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
236 
237  signal DISPREG : slv16 := (others=>'0');
238  signal STATLEDS : slv8 := (others=>'0');
239  signal ABCLKDIV : slv16 := (others=>'0');
240 
241  signal SWI : slv8 := (others=>'0');
242  signal BTN : slv5 := (others=>'0');
243  signal LED : slv8 := (others=>'0');
244  signal DSP_DAT : slv16 := (others=>'0');
245  signal DSP_DP : slv4 := (others=>'0');
246 
247  constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
248  constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
249 
250 begin
251 
252  assert (sys_conf_clksys mod 1000000) = 0
253  report "assert sys_conf_clksys on MHz grid"
254  severity failure;
255 
256  GEN_CLKSYS : s6_cmt_sfs -- clock generator -------------------
257  generic map (
258  VCO_DIVIDE => sys_conf_clksys_vcodivide ,
259  VCO_MULTIPLY => sys_conf_clksys_vcomultiply ,
260  OUT_DIVIDE => sys_conf_clksys_outdivide ,
261  CLKIN_PERIOD => 10.0,
262  CLKIN_JITTER => 0.01,
263  STARTUP_WAIT => false,
264  GEN_TYPE => sys_conf_clksys_gentype )
265  port map (
266  CLKIN => I_CLK100,
267  CLKFX => CLK,
268  LOCKED => open
269  );
270 
271  CLKDIV : clkdivce -- usec/msec clock divider -----------
272  generic map (
273  CDUWIDTH => 7,
274  USECDIV => sys_conf_clksys_mhz ,
275  MSECDIV => 1000)
276  port map (
277  CLK => CLK,
278  CE_USEC => CE_USEC,
279  CE_MSEC => CE_MSEC
280  );
281 
282  IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
283  port map (
284  CLK => CLK,
285  RESET => '0',
286  SEL => SWI(0),
287  RXD => RXD,
288  TXD => TXD,
289  CTS_N => CTS_N,
290  RTS_N => RTS_N,
291  I_RXD0 => I_RXD,
292  O_TXD0 => O_TXD,
293  I_RXD1 => I_FUSP_RXD ,
294  O_TXD1 => O_FUSP_TXD ,
295  I_CTS1_N => I_FUSP_CTS_N ,
296  O_RTS1_N => O_FUSP_RTS_N
297  );
298 
299  RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
300  generic map (
301  BTOWIDTH => 7, -- 128 cycles access timeout
302  RTAWIDTH => 12,
303  SYSID => (others =>'0'),
304  IFAWIDTH => 5, -- 32 word input fifo
305  OFAWIDTH => 5, -- 32 word output fifo
306  PETOWIDTH => sys_conf_fx2_petowidth,
307  CCWIDTH => sys_conf_fx2_ccwidth ,
308  ENAPIN_RLMON => sbcntl_sbf_rlmon ,
309  ENAPIN_RBMON => sbcntl_sbf_rbmon ,
310  CDWIDTH => 13,
311  CDINIT => sys_conf_ser2rri_cdinit,
312  RBMON_AWIDTH => sys_conf_rbmon_awidth ,
313  RBMON_RBADDR => rbaddr_rbmon)
314  port map (
315  CLK => CLK,
316  CE_USEC => CE_USEC,
317  CE_MSEC => CE_MSEC,
318  CE_INT => CE_MSEC,
319  RESET => RESET,
320  ENAXON => SWI(1),
321  ENAFX2 => SWI(2),
322  RXSD => RXD,
323  TXSD => TXD,
324  CTS_N => CTS_N,
325  RTS_N => RTS_N,
326  RB_MREQ => RB_MREQ,
327  RB_SRES => RB_SRES,
328  RB_LAM => RB_LAM,
329  RB_STAT => RB_STAT,
330  RL_MONI => open,
331  RLB_MONI => RLB_MONI,
332  SER_MONI => SER_MONI,
333  FX2_MONI => FX2_MONI,
334  I_FX2_IFCLK => I_FX2_IFCLK,
335  O_FX2_FIFO => O_FX2_FIFO,
336  I_FX2_FLAG => I_FX2_FLAG,
337  O_FX2_SLRD_N => O_FX2_SLRD_N,
338  O_FX2_SLWR_N => O_FX2_SLWR_N,
339  O_FX2_SLOE_N => O_FX2_SLOE_N,
340  O_FX2_PKTEND_N => O_FX2_PKTEND_N,
341  IO_FX2_DATA => IO_FX2_DATA
342  );
343 
344  SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
345  port map (
346  CLK => CLK,
347  RESET => RESET,
348  RB_MREQ => RB_MREQ,
349  RB_SRES => RB_SRES_CPU ,
350  RB_STAT => RB_STAT,
351  RB_LAM_CPU => RB_LAM(0),
352  GRESET => GRESET,
353  CRESET => CRESET,
354  BRESET => BRESET,
355  CP_STAT => CP_STAT,
356  EI_PRI => EI_PRI,
357  EI_VECT => EI_VECT,
358  EI_ACKM => EI_ACKM,
359  ITIMER => ITIMER,
360  IB_MREQ => IB_MREQ,
361  IB_SRES => IB_SRES_IBDR ,
362  MEM_REQ => MEM_REQ,
363  MEM_WE => MEM_WE,
364  MEM_BUSY => MEM_BUSY,
365  MEM_ACK_R => MEM_ACK_R,
366  MEM_ADDR => MEM_ADDR,
367  MEM_BE => MEM_BE,
368  MEM_DI => MEM_DI,
369  MEM_DO => MEM_DO,
370  DM_STAT_DP => DM_STAT_DP
371  );
372 
373  IBDR_SYS : ibdr_maxisys -- IO system -------------------------
374  port map (
375  CLK => CLK,
376  CE_USEC => CE_USEC,
377  CE_MSEC => CE_MSEC,
378  RESET => GRESET,
379  BRESET => BRESET,
380  ITIMER => ITIMER,
381  CPUSUSP => CP_STAT.cpususp ,
382  RB_LAM => RB_LAM(15 downto 1),
383  IB_MREQ => IB_MREQ,
384  IB_SRES => IB_SRES_IBDR ,
385  EI_ACKM => EI_ACKM,
386  EI_PRI => EI_PRI,
387  EI_VECT => EI_VECT,
388  DISPREG => DISPREG
389  );
390 
391  MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
392 
393  SRAM_CTL: nx_cram_memctl_as -- memory controller -----------------
394  generic map (
395  READ0DELAY => sys_conf_memctl_read0delay ,
396  READ1DELAY => sys_conf_memctl_read1delay ,
397  WRITEDELAY => sys_conf_memctl_writedelay )
398  port map (
399  CLK => CLK,
400  RESET => GRESET,
401  REQ => MEM_REQ ,
402  WE => MEM_WE ,
403  BUSY => MEM_BUSY ,
404  ACK_R => MEM_ACK_R ,
405  ACK_W => open,
406  ACT_R => MEM_ACT_R ,
407  ACT_W => MEM_ACT_W ,
408  ADDR => MEM_ADDR_EXT ,
409  BE => MEM_BE ,
410  DI => MEM_DI ,
411  DO => MEM_DO ,
412  O_MEM_CE_N => O_MEM_CE_N,
413  O_MEM_BE_N => O_MEM_BE_N,
414  O_MEM_WE_N => O_MEM_WE_N,
415  O_MEM_OE_N => O_MEM_OE_N,
416  O_MEM_ADV_N => O_MEM_ADV_N,
417  O_MEM_CLK => O_MEM_CLK,
418  O_MEM_CRE => O_MEM_CRE,
419  I_MEM_WAIT => I_MEM_WAIT,
420  O_MEM_ADDR => O_MEM_ADDR,
421  IO_MEM_DATA => IO_MEM_DATA
422  );
423 
424  O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
425  O_PPCM_RST_N <= '1'; --
426 
427  LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
428  port map (
429  CLK => CLK,
430  CE_USEC => CE_USEC,
431  RESET => GRESET,
432  ENAFX2 => SWI(2),
433  RB_SRES => RB_SRES,
434  RLB_MONI => RLB_MONI,
435  SER_MONI => SER_MONI,
436  IOLEDS => DSP_DP
437  );
438 
439  ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
440 
441  HIO70 : pdp11_hio70 -- hio from sys70 --------------------
442  generic map (
443  LWIDTH => LED'length ,
444  DCWIDTH => 2)
445  port map (
446  SEL_LED => SWI(3),
447  SEL_DSP => SWI(5 downto 4),
448  MEM_ACT_R => MEM_ACT_R,
449  MEM_ACT_W => MEM_ACT_W,
450  CP_STAT => CP_STAT,
451  DM_STAT_DP => DM_STAT_DP,
452  ABCLKDIV => ABCLKDIV,
453  DISPREG => DISPREG,
454  LED => LED,
455  DSP_DAT => DSP_DAT
456  );
457 
458  HIO : sn_humanio_rbus -- hio manager -----------------------
459  generic map (
460  BWIDTH => 5,
461  DEBOUNCE => sys_conf_hio_debounce ,
462  RB_ADDR => rbaddr_hio)
463  port map (
464  CLK => CLK,
465  RESET => RESET,
466  CE_MSEC => CE_MSEC,
467  RB_MREQ => RB_MREQ,
468  RB_SRES => RB_SRES_HIO ,
469  SWI => SWI,
470  BTN => BTN,
471  LED => LED,
472  DSP_DAT => DSP_DAT,
473  DSP_DP => DSP_DP,
474  I_SWI => I_SWI,
475  I_BTN => I_BTN,
476  O_LED => O_LED,
477  O_ANO_N => O_ANO_N,
478  O_SEG_N => O_SEG_N
479  );
480 
481  RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
482  port map (
483  RB_SRES_1 => RB_SRES_CPU,
484  RB_SRES_2 => RB_SRES_HIO,
485  RB_SRES_OR => RB_SRES
486  );
487 
488 end syn;
slv8 :=( others =>'0' ) LED
slv16 :=x"fef0" rbaddr_hio
slv32 :=( others =>'0' ) MEM_DI
rlink_sp1c_fx2 rlinkrlink
slv4 :=( others =>'0' ) RB_STAT
slbit :='0' CTS_N
Definition: xlib.vhd:40
in I_FUSP_RXDslbit
out O_MEM_ADDRslv23
dm_stat_dp_type :=dm_stat_dp_init DM_STAT_DP
Definition: iblib.vhd:36
out O_MEM_CE_Nslbit
ib_mreq_type :=ib_mreq_init IB_MREQ
slv20 :=( others =>'0' ) MEM_ADDR
slbit :='0' MEM_ACT_W
slv3 :=( others =>'0' ) EI_PRI
cp_stat_type :=cp_stat_init CP_STAT
slv16 :=( others =>'0' ) RB_LAM
slv8 :=( others =>'0' ) STATLEDS
inout IO_FX2_DATAslv8
out O_FX2_SLRD_Nslbit
slbit :='0' RESET
slbit :='0' MEM_REQ
slv16 :=x"ffe8" rbaddr_rbmon
bp_rs232_2l4l_iob iob_rs232iob_rs232
ioleds_sp1c_fx2 led_ioled_io
in I_CLK100slbit
in I_MEM_WAITslbit
pdp11_sys70 sys70sys70
out O_PPCM_CE_Nslbit
out O_FUSP_RTS_Nslbit
rb_mreq_type :=rb_mreq_init RB_MREQ
out O_FX2_FIFOslv2
slbit :='0' ITIMER
out O_MEM_CLKslbit
slv4 :=( others =>'0' ) DSP_DP
s6_cmt_sfs gen_clksysgen_clksys
rb_sres_type :=rb_sres_init RB_SRES_HIO
slbit :='0' MEM_ACK_R
out O_MEM_BE_Nslv2
slbit :='0' RTS_N
inout IO_MEM_DATAslv16
sn_humanio_rbus hiohio
Definition: pdp11.vhd:107
out O_MEM_ADV_Nslbit
slbit :='0' CLK
out O_FX2_PKTEND_Nslbit
slbit :='0' MEM_ACT_R
slbit :='0' TXD
_library_ ieeeieee
slv22 :=( others =>'0' ) MEM_ADDR_EXT
slbit :='0' CRESET
slv8 :=( others =>'0' ) SWI
ibdr_maxisys ibdr_sysibdr_sys
slv5 :=( others =>'0' ) BTN
ib_sres_type :=ib_sres_init IB_SRES_IBDR
slbit :='0' MEM_WE
slbit :='0' CE_MSEC
slbit :='0' CE_USEC
in I_FUSP_CTS_Nslbit
out O_MEM_WE_Nslbit
slbit :='0' EI_ACKM
out O_FX2_SLWR_Nslbit
slbit :='0' MEM_BUSY
out O_TXDslbit
nx_cram_memctl_as sram_ctlsram_ctl
out O_MEM_CREslbit
rb_sres_type :=rb_sres_init RB_SRES
slv4 :=( others =>'0' ) MEM_BE
serport_moni_type :=serport_moni_init SER_MONI
slv16 :=( others =>'0' ) DSP_DAT
out O_FX2_SLOE_Nslbit
out O_ANO_Nslv4
slv32 :=( others =>'0' ) MEM_DO
Definition: rblib.vhd:41
in I_FX2_FLAGslv4
slbit :='0' BRESET
clkdivce clkdivclkdiv
rb_sres_or_2 rb_sres_orrb_sres_or
slv16 :=( others =>'0' ) ABCLKDIV
in I_SWIslv8
slv16 :=( others =>'0' ) DISPREG
out O_LEDslv8
slbit :='1' RXD
rb_sres_type :=rb_sres_init RB_SRES_CPU
in I_BTNslv5
rlb_moni_type :=rlb_moni_init RLB_MONI
slv9_2 :=( others =>'0' ) EI_VECT
in I_FX2_IFCLKslbit
fx2ctl_moni_type :=fx2ctl_moni_init FX2_MONI
out O_SEG_Nslv8
in I_RXDslbit
out O_MEM_OE_Nslbit
slbit :='0' GRESET
pdp11_hio70 hio70hio70
out O_PPCM_RST_Nslbit
out O_FUSP_TXDslbit