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W11 CPU core and support modules
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rlinklib.vhd
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1-- $Id: rlinklib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: rlinklib
7-- Description: Definitions for rlink interface and bus entities
8--
9-- Dependencies: -
10-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.35
11--
12-- Revision History:
13-- Date Rev Version Comment
14--
15-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
16-- 2016-03-28 755 4.2 add rlink_sp2c
17-- 2015-04-11 666 4.1.2 rlink_core8: add ESC(XON|FILL);
18-- rlink_sp1c: rename ENAESC->ESCFILL
19-- 2015-02-21 649 4.1.1 add ioleds_sp1c
20-- 2014-12-21 617 4.1 use stat(2) to signal rbus timeout
21-- 2014-10-12 596 4.0 now rlink v4.0 iface, 4 bit STAT
22-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
23-- 2013-04-21 509 3.3.2 add rlb_moni record definition
24-- 2012-12-29 466 3.3.1 add rlink_rlbmux
25-- 2011-12-23 444 3.3 CLK_CYCLE now integer
26-- 2011-12-21 442 3.2.1 retire old, deprecated interfaces
27-- 2011-12-09 437 3.2 add rlink_core8
28-- 2011-11-18 427 3.1.3 now numeric_std clean
29-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
30-- new rlink_serport interface;
31-- rename rlink_core_serport->rlink_base_serport
32-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
33-- 2010-12-22 346 3.1 rename: [cd]crc->[cd]err, ioto->rbnak, ioerr->rberr
34-- 2010-12-04 343 3.0 move rbus components to rbus/rblib; renames
35-- rri_ -> rlink and c_rri -> c_rlink;
36-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
37-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
38-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport
39-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
40-- drop RP_IINT from interfaces; drop RTSFLUSH generic
41-- 2010-05-01 285 2.1.3 remove rri_rb_rpcompat, now obsolete
42-- 2010-04-18 279 2.1.2 rri_core_serport: drop RTSFBUF generic
43-- 2010-04-10 275 2.1.1 add rri_core_serport
44-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core, rri_serport;
45-- CE_USEC, RTSFLUSH, CTS_N, RTS_N for rri_serport
46-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
47-- 2008-08-22 161 1.3 renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
48-- 2008-02-16 116 1.2.1 added rri_wreg(rw|w|r)_3
49-- 2008-01-20 113 1.2 added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
50-- 2007-11-24 98 1.1 added RP_IINT for rri_core.
51-- 2007-09-09 81 1.0 Initial version
52------------------------------------------------------------------------------
53
54library ieee;
55use ieee.std_logic_1164.all;
56use ieee.numeric_std.all;
57
58use work.slvtypes.all;
59use work.rblib.all;
60use work.rbdlib.all;
61use work.serportlib.all;
62
63package rlinklib is
64
65constant c_rlink_dat_sop : slv9 := "100000000";
66constant c_rlink_dat_eop : slv9 := "100000001";
67constant c_rlink_dat_nak : slv9 := "100000010";
68constant c_rlink_dat_attn : slv9 := "100000011";
69
70constant c_rlink_cmd_rreg : slv3 := "000";
71constant c_rlink_cmd_rblk : slv3 := "001";
72constant c_rlink_cmd_wreg : slv3 := "010";
73constant c_rlink_cmd_wblk : slv3 := "011";
74constant c_rlink_cmd_labo : slv3 := "100";
75constant c_rlink_cmd_attn : slv3 := "101";
76constant c_rlink_cmd_init : slv3 := "110";
77
78subtype c_rlink_cmd_rbf_seq is integer range 7 downto 3; -- sequence number
79subtype c_rlink_cmd_rbf_code is integer range 2 downto 0; -- command code
80
81subtype c_rlink_stat_rbf_stat is integer range 7 downto 4; -- ext status bits
82constant c_rlink_stat_rbf_attn: integer := 3; -- attention flags set
83constant c_rlink_stat_rbf_rbtout: integer := 2; -- rbus timeout
84constant c_rlink_stat_rbf_rbnak: integer := 1; -- rbus no ack
85constant c_rlink_stat_rbf_rberr: integer := 0; -- rbus err bit set
86
87constant c_rlink_nakcode_ccrc : slv3 := "000"; -- cmd crc error
88constant c_rlink_nakcode_dcrc : slv3 := "001"; -- data crc error
89constant c_rlink_nakcode_frame : slv3 := "010"; -- framing error
90constant c_rlink_nakcode_unused : slv3 := "011"; -- <unused code>
91constant c_rlink_nakcode_cmd : slv3 := "100"; -- bad cmd
92constant c_rlink_nakcode_cnt : slv3 := "101"; -- bad cnt
93constant c_rlink_nakcode_rtovfl : slv3 := "110"; -- rtbuf ovfl
94constant c_rlink_nakcode_rtwblk : slv3 := "111"; -- rtbuf ovfl in wblk
95
96type rl_moni_type is record -- rlink_core monitor port
97 eop : slbit; -- eop send in last cycle
98 attn : slbit; -- attn send in last cycle
99 lamp : slbit; -- attn (lam) pending
100end record rl_moni_type;
101
103 ('0','0','0'); -- eop,attn,lamp
104
105type rlb_moni_type is record -- rlink 8b monitor port
106 rxval : slbit; -- data in valid
107 rxhold : slbit; -- data in hold
108 txena : slbit; -- data out enable
109 txbusy : slbit; -- data out busy
110end record rlb_moni_type;
111
113 ('0','0','0','0'); -- rxval,rxhold,txena,txbusy
114
115-- these definitions logically belongs into the 'for test benches' section'
116-- it is here for convenience to simplify instantiations.
117constant sbcntl_sbf_rlmon : integer := 15;
118constant sbcntl_sbf_rlbmon : integer := 14;
119
120component rlink_core is -- rlink core with 9bit iface
121 generic (
122 BTOWIDTH : positive := 5; -- rbus timeout counter width
123 RTAWIDTH : positive := 12; -- retransmit buffer address width
124 SYSID : slv32 := (others=>'0'); -- rlink system id
125 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
126 ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
127 port (
128 CLK : in slbit; -- clock
129 CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
130 RESET : in slbit; -- reset
131 RL_DI : in slv9; -- rlink 9b: data in
132 RL_ENA : in slbit; -- rlink 9b: data enable
133 RL_BUSY : out slbit; -- rlink 9b: data busy
134 RL_DO : out slv9; -- rlink 9b: data out
135 RL_VAL : out slbit; -- rlink 9b: data valid
136 RL_HOLD : in slbit; -- rlink 9b: data hold
137 RL_MONI : out rl_moni_type; -- rlink: monitor port
138 RB_MREQ : out rb_mreq_type; -- rbus: request
139 RB_SRES : in rb_sres_type; -- rbus: response
140 RB_LAM : in slv16; -- rbus: look at me
141 RB_STAT : in slv4 -- rbus: status flags
142 );
143end component;
144
145component rlink_aif is -- rlink, abstract interface
146 port (
147 CLK : in slbit; -- clock
148 CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
149 RESET : in slbit :='0'; -- reset
150 RL_DI : in slv9; -- rlink 9b: data in
151 RL_ENA : in slbit; -- rlink 9b: data enable
152 RL_BUSY : out slbit; -- rlink 9b: data busy
153 RL_DO : out slv9; -- rlink 9b: data out
154 RL_VAL : out slbit; -- rlink 9b: data valid
155 RL_HOLD : in slbit := '0' -- rlink 9b: data hold
156 );
157end component;
158
159component rlink_core8 is -- rlink core with 8bit iface
160 generic (
161 BTOWIDTH : positive := 5; -- rbus timeout counter width
162 RTAWIDTH : positive := 12; -- retransmit buffer address width
163 SYSID : slv32 := (others=>'0'); -- rlink system id
164 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
165 ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
166 ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
167 port (
168 CLK : in slbit; -- clock
169 CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
170 RESET : in slbit; -- reset
171 ESCXON : in slbit := '0'; -- enable xon/xoff escaping
172 ESCFILL : in slbit := '0'; -- enable fill escaping
173 RLB_DI : in slv8; -- rlink 8b: data in
174 RLB_ENA : in slbit; -- rlink 8b: data enable
175 RLB_BUSY : out slbit; -- rlink 8b: data busy
176 RLB_DO : out slv8; -- rlink 8b: data out
177 RLB_VAL : out slbit; -- rlink 8b: data valid
178 RLB_HOLD : in slbit; -- rlink 8b: data hold
179 RL_MONI : out rl_moni_type; -- rlink: monitor port
180 RB_MREQ : out rb_mreq_type; -- rbus: request
181 RB_SRES : in rb_sres_type; -- rbus: response
182 RB_LAM : in slv16; -- rbus: look at me
183 RB_STAT : in slv4 -- rbus: status flags
184 );
185end component;
186
187component rlink_rlbmux is -- rlink rlb multiplexer
188 port (
189 SEL : in slbit; -- port select (0:RLB<->P0; 1:RLB<->P1)
190 RLB_DI : out slv8; -- rlb: data in
191 RLB_ENA : out slbit; -- rlb: data enable
192 RLB_BUSY : in slbit; -- rlb: data busy
193 RLB_DO : in slv8; -- rlb: data out
194 RLB_VAL : in slbit; -- rlb: data valid
195 RLB_HOLD : out slbit; -- rlb: data hold
196 P0_RXDATA : in slv8; -- p0: rx data
197 P0_RXVAL : in slbit; -- p0: rx valid
198 P0_RXHOLD : out slbit; -- p0: rx hold
199 P0_TXDATA : out slv8; -- p0: tx data
200 P0_TXENA : out slbit; -- p0: tx enable
201 P0_TXBUSY : in slbit; -- p0: tx busy
202 P1_RXDATA : in slv8; -- p1: rx data
203 P1_RXVAL : in slbit; -- p1: rx valid
204 P1_RXHOLD : out slbit; -- p1: rx hold
205 P1_TXDATA : out slv8; -- p1: tx data
206 P1_TXENA : out slbit; -- p1: tx enable
207 P1_TXBUSY : in slbit -- p1: tx busy
208 );
209end component;
210
211--
212-- core + concrete_interface combo's
213--
214
215component rlink_sp1c is -- rlink_core8+serport_1clock combo
216 generic (
217 BTOWIDTH : positive := 5; -- rbus timeout counter width
218 RTAWIDTH : positive := 12; -- retransmit buffer address width
219 SYSID : slv32 := (others=>'0'); -- rlink system id
220 IFAWIDTH : natural := 5; -- input fifo address width (0=none)
221 OFAWIDTH : natural := 5; -- output fifo address width (0=none)
222 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
223 ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
224 ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
225 CDWIDTH : positive := 13; -- clk divider width
226 CDINIT : natural := 15; -- clk divider initial/reset setting
227 RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
228 RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
229 port (
230 CLK : in slbit; -- clock
231 CE_USEC : in slbit; -- 1 usec clock enable
232 CE_MSEC : in slbit; -- 1 msec clock enable
233 CE_INT : in slbit := '0'; -- rri ato time unit clock enable
234 RESET : in slbit; -- reset
235 ENAXON : in slbit := '0'; -- enable xon/xoff handling
236 ESCFILL : in slbit := '0'; -- enable fill escaping
237 RXSD : in slbit; -- receive serial data (board view)
238 TXSD : out slbit; -- transmit serial data (board view)
239 CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
240 RTS_N : out slbit; -- request to send (act.low, board view)
241 RB_MREQ : out rb_mreq_type; -- rbus: request
242 RB_SRES : in rb_sres_type; -- rbus: response
243 RB_LAM : in slv16; -- rbus: look at me
244 RB_STAT : in slv4; -- rbus: status flags
245 RL_MONI : out rl_moni_type; -- rlink_core: monitor port
246 SER_MONI : out serport_moni_type -- serport: monitor port
247 );
248end component;
249
250component rlink_sp2c is -- rlink_core8+serport_2clock2 combo
251 generic (
252 BTOWIDTH : positive := 5; -- rbus timeout counter width
253 RTAWIDTH : positive := 12; -- retransmit buffer address width
254 SYSID : slv32 := (others=>'0'); -- rlink system id
255 IFAWIDTH : natural := 5; -- input fifo address width (0=none)
256 OFAWIDTH : natural := 5; -- output fifo address width (0=none)
257 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
258 ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
259 ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
260 CDWIDTH : positive := 13; -- clk divider width
261 CDINIT : natural := 15; -- clk divider initial/reset setting
262 RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
263 RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
264 port (
265 CLK : in slbit; -- U|clock (user design)
266 CE_USEC : in slbit; -- U|1 usec clock enable
267 CE_MSEC : in slbit; -- U|1 msec clock enable
268 CE_INT : in slbit := '0'; -- U|rri ato time unit clock enable
269 RESET : in slbit; -- U|reset
270 CLKS : in slbit; -- S|clock (frontend:serial)
271 CES_MSEC : in slbit; -- S|1 msec clock enable
272 ENAXON : in slbit; -- U|enable xon/xoff handling
273 ESCFILL : in slbit; -- U|enable fill escaping
274 RXSD : in slbit; -- S|receive serial data (board view)
275 TXSD : out slbit; -- S|transmit serial data (board view)
276 CTS_N : in slbit := '0'; -- S|clear to send (act.low, board view)
277 RTS_N : out slbit; -- S|request to send (act.low, brd view)
278 RB_MREQ : out rb_mreq_type; -- U|rbus: request
279 RB_SRES : in rb_sres_type; -- U|rbus: response
280 RB_LAM : in slv16; -- U|rbus: look at me
281 RB_STAT : in slv4; -- U|rbus: status flags
282 RL_MONI : out rl_moni_type; -- U|rlink_core: monitor port
283 SER_MONI : out serport_moni_type -- U|serport: monitor port
284 );
285end component;
286--
287-- io activity leds
288--
289component ioleds_sp1c -- io activity leds for rlink_sp1c
290 port (
291 SER_MONI : in serport_moni_type; -- ser: monitor port
292 IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
293 );
294end component;
295
296--
297-- components for use in test benches (not synthesizable)
298--
299
300component rlink_mon is -- rlink monitor
301 generic (
302 DWIDTH : positive := 9); -- data port width (8 or 9)
303 port (
304 CLK : in slbit; -- clock
305 CLK_CYCLE : in integer := 0; -- clock cycle number
306 ENA : in slbit := '1'; -- enable monitor output
307 RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
308 RL_ENA : in slbit; -- rlink: data enable
309 RL_BUSY : in slbit; -- rlink: data busy
310 RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
311 RL_VAL : in slbit; -- rlink: data valid
312 RL_HOLD : in slbit -- rlink: data hold
313 );
314end component;
315
316component rlink_mon_sb is -- simbus wrap for rlink monitor
317 generic (
318 DWIDTH : positive := 9; -- data port width (8 or 9)
319 ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
320 port (
321 CLK : in slbit; -- clock
322 RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
323 RL_ENA : in slbit; -- rlink: data enable
324 RL_BUSY : in slbit; -- rlink: data busy
325 RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
326 RL_VAL : in slbit; -- rlink: data valid
327 RL_HOLD : in slbit -- rlink: data hold
328 );
329end component;
330
331end package rlinklib;
in SER_MONI serport_moni_type
Definition: ioleds_sp1c.vhd:30
out IOLEDS slv4
Definition: ioleds_sp1c.vhd:32
Definition: rblib.vhd:32
integer range 2 downto 0 c_rlink_cmd_rbf_code
Definition: rlinklib.vhd:79
rl_moni_type
Definition: rlinklib.vhd:96
slv9 := "100000011" c_rlink_dat_attn
Definition: rlinklib.vhd:68
slv3 := "011" c_rlink_nakcode_unused
Definition: rlinklib.vhd:90
slv9 := "100000000" c_rlink_dat_sop
Definition: rlinklib.vhd:65
integer := 3 c_rlink_stat_rbf_attn
Definition: rlinklib.vhd:82
slv3 := "000" c_rlink_nakcode_ccrc
Definition: rlinklib.vhd:87
slv3 := "111" c_rlink_nakcode_rtwblk
Definition: rlinklib.vhd:94
slv9 := "100000001" c_rlink_dat_eop
Definition: rlinklib.vhd:66
slv3 := "100" c_rlink_cmd_labo
Definition: rlinklib.vhd:74
slv3 := "011" c_rlink_cmd_wblk
Definition: rlinklib.vhd:73
rl_moni_type :=( '0', '0', '0') rl_moni_init
Definition: rlinklib.vhd:102
slv3 := "110" c_rlink_nakcode_rtovfl
Definition: rlinklib.vhd:93
slv3 := "101" c_rlink_cmd_attn
Definition: rlinklib.vhd:75
integer := 15 sbcntl_sbf_rlmon
Definition: rlinklib.vhd:117
integer := 0 c_rlink_stat_rbf_rberr
Definition: rlinklib.vhd:85
slv3 := "001" c_rlink_nakcode_dcrc
Definition: rlinklib.vhd:88
slv3 := "010" c_rlink_nakcode_frame
Definition: rlinklib.vhd:89
slv9 := "100000010" c_rlink_dat_nak
Definition: rlinklib.vhd:67
integer range 7 downto 3 c_rlink_cmd_rbf_seq
Definition: rlinklib.vhd:78
slv3 := "000" c_rlink_cmd_rreg
Definition: rlinklib.vhd:70
slv3 := "110" c_rlink_cmd_init
Definition: rlinklib.vhd:76
slv3 := "001" c_rlink_cmd_rblk
Definition: rlinklib.vhd:71
slv3 := "101" c_rlink_nakcode_cnt
Definition: rlinklib.vhd:92
integer range 7 downto 4 c_rlink_stat_rbf_stat
Definition: rlinklib.vhd:81
slv3 := "010" c_rlink_cmd_wreg
Definition: rlinklib.vhd:72
rlb_moni_type :=( '0', '0', '0', '0') rlb_moni_init
Definition: rlinklib.vhd:112
slv3 := "100" c_rlink_nakcode_cmd
Definition: rlinklib.vhd:91
integer := 2 c_rlink_stat_rbf_rbtout
Definition: rlinklib.vhd:83
integer := 1 c_rlink_stat_rbf_rbnak
Definition: rlinklib.vhd:84
integer := 14 sbcntl_sbf_rlbmon
Definition: rlinklib.vhd:118
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31