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W11 CPU core and support modules
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pdp11_sys70.vhd
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1-- $Id: pdp11_sys70.vhd 1348 2023-01-08 13:33:01Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_sys70 - syn
7-- Description: pdp11: 11/70 system - single core +rbus,debug,cache
8--
9-- Dependencies: w11a/pdp11_core_rbus
10-- w11a/pdp11_core
11-- w11a/pdp11_cache
12-- w11a/pdp11_mem70
13-- ibus/ibd_ibmon
14-- ibus/ibd_ibtst
15-- ibus/ib_sres_or_4
16-- w11a/pdp11_dmscnt
17-- w11a/pdp11_dmcmon
18-- w11a/pdp11_dmhpbt
19-- w11a/pdp11_dmpcnt
20-- rbus/rb_sres_or_4
21-- rbus/rb_sres_or_2
22-- w11a/pdp11_tmu_sb [sim only]
23--
24-- Test bench: tb/tb_pdp11_core (implicit)
25-- Target Devices: generic
26-- Tool versions: ise 14.7; viv 2014.4-2022.1; ghdl 0.33-2.0.0
27--
28-- Revision History:
29-- Date Rev Version Comment
30-- 2023-01-08 1348 1.3.5 pass DM_STAT_SE to pdp11_tmu_sb
31-- 2022-12-12 1330 1.3.4 dm_stat_se_type: rename vfetch -> vstart
32-- 2019-06-02 1159 1.3.3 use rbaddr_ constants
33-- 2019-03-02 1116 1.3.2 add RESET_SYS; fix pdp11_mem70 reset
34-- 2019-02-16 1112 1.3.1 add ibd_ibtst
35-- 2018-10-13 1055 1.3 drop ITIMER,DM_STAT_DP out ports, use DM_STAT_EXP
36-- add PERFEXT in port
37-- 2018-10-06 1053 1.2.3 drop DM_STAT_SY; add DM_STAT_CA; use _SE.pcload
38-- 2018-09-29 1051 1.2.2 add pdp11_dmpcnt
39-- 2017-04-22 884 1.2.1 pdp11_dmcmon: use SNUM and AWIDTH generics
40-- 2016-03-22 750 1.2 pdp11_cache now configurable size
41-- 2015-11-01 712 1.1.4 use sbcntl_sbf_tmu
42-- 2015-07-19 702 1.1.3 use DM_STAT_SE
43-- 2015-07-04 697 1.1.2 change DM_STAT_SY setup; add dmcmon, dmhbpt;
44-- 2015-06-26 695 1.1.1 add pdp11_dmscnt support
45-- 2015-05-09 677 1.1 start/stop/suspend overhaul; reset overhaul
46-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*)
47------------------------------------------------------------------------------
48
49library ieee;
50use ieee.std_logic_1164.all;
51use ieee.numeric_std.all;
52
53use work.slvtypes.all;
54use work.rblib.all;
55use work.pdp11.all;
56use work.iblib.all;
57use work.sys_conf.all;
58
59-- ----------------------------------------------------------------------------
60
61entity pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
62 port (
63 CLK : in slbit; -- clock
64 RESET : in slbit; -- reset
65 RB_MREQ : in rb_mreq_type; -- rbus request (slave)
66 RB_SRES : out rb_sres_type; -- rbus response
67 RB_STAT : out slv4; -- rbus status flags
68 RB_LAM_CPU : out slbit; -- rbus lam (cpu)
69 GRESET : out slbit; -- general reset (from rbus)
70 CRESET : out slbit; -- cpu reset (from cp)
71 BRESET : out slbit; -- bus reset (from cp or cpu)
72 CP_STAT : out cp_stat_type; -- console port status
73 EI_PRI : in slv3; -- external interrupt priority
74 EI_VECT : in slv9_2; -- external interrupt vector
75 EI_ACKM : out slbit; -- external interrupt acknowledge
76 PERFEXT : in slv8; -- cpu external perf counter signals
77 IB_MREQ : out ib_mreq_type; -- ibus request (master)
78 IB_SRES : in ib_sres_type; -- ibus response
79 MEM_REQ : out slbit; -- memory: request
80 MEM_WE : out slbit; -- memory: write enable
81 MEM_BUSY : in slbit; -- memory: controller busy
82 MEM_ACK_R : in slbit; -- memory: acknowledge read
83 MEM_ADDR : out slv20; -- memory: address
84 MEM_BE : out slv4; -- memory: byte enable
85 MEM_DI : out slv32; -- memory: data in (memory view)
86 MEM_DO : in slv32; -- memory: data out (memory view)
87 DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports
88 );
89end pdp11_sys70;
90
91architecture syn of pdp11_sys70 is
92
93 signal RB_SRES_CORE : rb_sres_type := rb_sres_init;
94 signal RB_SRES_DMSCNT : rb_sres_type := rb_sres_init;
95 signal RB_SRES_DMPCNT : rb_sres_type := rb_sres_init;
96 signal RB_SRES_DMHBPT : rb_sres_type := rb_sres_init;
97 signal RB_SRES_DMCMON : rb_sres_type := rb_sres_init;
98 signal RB_SRES_DM : rb_sres_type := rb_sres_init;
99 signal RB_SRES_L : rb_sres_type := rb_sres_init;
100
101 signal CP_CNTL : cp_cntl_type := cp_cntl_init;
102 signal CP_ADDR : cp_addr_type := cp_addr_init;
103 signal CP_DIN : slv16 := (others=>'0');
104 signal CP_STAT_L : cp_stat_type := cp_stat_init;
105 signal CP_DOUT : slv16 := (others=>'0');
106
107 signal EI_ACKM_L : slbit := '0';
108
109 signal EM_MREQ : em_mreq_type := em_mreq_init;
110 signal EM_SRES : em_sres_type := em_sres_init;
111
112 signal GRESET_L : slbit := '0'; -- general reset (from rbus init)
113 signal CRESET_L : slbit := '0'; -- cpu reset (from -creset command)
114 signal BRESET_L : slbit := '0'; -- bus reset (RESET inst or -breset)
115
116 signal RESET_SYS : slbit := '0'; -- or of RESET (port) and GRESET (rbus)
117
118 signal HM_ENA : slbit := '0';
119 signal MEM70_FMISS : slbit := '0';
120 signal CACHE_FMISS : slbit := '0';
121
122 signal HBPT : slbit := '0';
123
124 signal DM_STAT_SE : dm_stat_se_type := dm_stat_se_init;
125 signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
126 signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
127 signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
128 signal DM_STAT_CA : dm_stat_ca_type := dm_stat_ca_init;
129
130 signal IB_MREQ_M : ib_mreq_type := ib_mreq_init;
131 signal IB_SRES_M : ib_sres_type := ib_sres_init;
132 signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
133 signal IB_SRES_IBMON : ib_sres_type := ib_sres_init;
134 signal IB_SRES_IBTST : ib_sres_type := ib_sres_init;
135
136 constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx
137 constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx
138
139begin
140
141 RB2CP : pdp11_core_rbus
142 generic map (
145 port map (
146 CLK => CLK,
147 RESET => RESET,
148 RB_MREQ => RB_MREQ,
150 RB_STAT => RB_STAT,
152 GRESET => GRESET_L,
153 CP_CNTL => CP_CNTL,
154 CP_ADDR => CP_ADDR,
155 CP_DIN => CP_DIN,
157 CP_DOUT => CP_DOUT
158 );
159
160 RESET_SYS <= RESET or GRESET_L; -- use as reset of w11 sub-system
161
162 W11A : pdp11_core
163 port map (
164 CLK => CLK,
165 RESET => RESET_SYS,
166 CP_CNTL => CP_CNTL,
167 CP_ADDR => CP_ADDR,
168 CP_DIN => CP_DIN,
170 CP_DOUT => CP_DOUT,
171 ESUSP_O => open,
172 ESUSP_I => '0',
173 HBPT => HBPT,
174 EI_PRI => EI_PRI,
175 EI_VECT => EI_VECT,
177 EM_MREQ => EM_MREQ,
178 EM_SRES => EM_SRES,
179 CRESET => CRESET_L,
180 BRESET => BRESET_L,
187 );
188
189 CACHE: pdp11_cache
190 generic map (
191 TWIDTH => sys_conf_cache_twidth)
192 port map (
193 CLK => CLK,
194 GRESET => RESET_SYS,
195 EM_MREQ => EM_MREQ,
196 EM_SRES => EM_SRES,
198 MEM_REQ => MEM_REQ,
199 MEM_WE => MEM_WE,
203 MEM_BE => MEM_BE,
204 MEM_DI => MEM_DI,
205 MEM_DO => MEM_DO,
207 );
208
209 MEM70: pdp11_mem70
210 port map (
211 CLK => CLK,
212 CRESET => CRESET_L,
213 HM_ENA => HM_ENA,
214 HM_VAL => DM_STAT_CA.rdhit,
218 );
219
220 HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
221 CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
222
223 IBMON : if sys_conf_ibmon_awidth > 0 generate
224 begin
225 I0 : ibd_ibmon
226 generic map (
227 IB_ADDR => slv(to_unsigned(8#160000#,16)),
228 AWIDTH => sys_conf_ibmon_awidth)
229 port map (
230 CLK => CLK,
231 RESET => RESET_SYS,
234 IB_SRES_SUM => DM_STAT_VM.ibsres
235 );
236 end generate IBMON;
237
238 IBTST : if sys_conf_ibtst generate
239 signal RESET_IBTST : slbit := '0';
240 begin
242 I0 : ibd_ibtst
243 generic map (
244 IB_ADDR => slv(to_unsigned(8#170000#,16)))
245 port map (
246 CLK => CLK,
250 );
251 end generate IBTST;
252
253 IB_SRES_OR : ib_sres_or_4
254 port map (
260 );
261
262 DMSCNT : if sys_conf_dmscnt generate
263 begin
264 I0: pdp11_dmscnt
265 generic map (
266 RB_ADDR => rbaddr_dmscnt_off)
267 port map (
268 CLK => CLK,
269 RESET => RESET_SYS,
270 RB_MREQ => RB_MREQ,
275 );
276 end generate DMSCNT;
277
278 DMCMON : if sys_conf_dmcmon_awidth > 0 generate
279 begin
280 I0: pdp11_dmcmon
281 generic map (
282 RB_ADDR => rbaddr_dmcmon_off,
283 AWIDTH => sys_conf_dmcmon_awidth,
284 SNUM => sys_conf_dmscnt)
285 port map (
286 CLK => CLK,
287 RESET => RESET_SYS,
288 RB_MREQ => RB_MREQ,
294 );
295 end generate DMCMON;
296
297 DMHBPT : if sys_conf_dmhbpt_nunit > 0 generate
298 begin
299 I0: pdp11_dmhbpt
300 generic map (
301 RB_ADDR => rbaddr_dmhbpt_off,
302 NUNIT => sys_conf_dmhbpt_nunit)
303 port map (
304 CLK => CLK,
305 RESET => RESET_SYS,
306 RB_MREQ => RB_MREQ,
312 HBPT => HBPT
313 );
314 end generate DMHBPT;
315
316 DMPCNT : if sys_conf_dmpcnt generate
317 signal PERFSIG : slv32 := (others=>'0');
318 begin
319 proc_sig: process (CP_STAT_L, DM_STAT_SE, DM_STAT_DP, DM_STAT_DP.psw,
321 DM_STAT_VM.ibmreq, DM_STAT_VM.ibsres, PERFEXT)
322 variable isig : slv32 := (others=>'0');
323 begin
324
325 isig := (others=>'0');
326
327 if DM_STAT_SE.cpbusy = '1' then
328 isig(0) := '1'; -- cpu_cpbusy
329 elsif CP_STAT_L.cpugo = '1' then
330 case DM_STAT_DP.psw.cmode is
331 when c_psw_kmode =>
332 if CP_STAT_L.cpuwait = '1' then
333 isig(3) := '1'; -- cpu_km_wait
334 elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
335 isig(2) := '1'; -- cpu_km_pri0
336 else
337 isig(1) := '1'; -- cpu_km_prix
338 end if;
339 when c_psw_smode =>
340 isig(4) := '1'; -- cpu_sm
341 when c_psw_umode =>
342 isig(5) := '1'; -- cpu_um
343 when others => null;
344 end case;
345 end if;
346
347 isig(6) := DM_STAT_SE.idec; -- cpu_idec
348 isig(7) := DM_STAT_SE.pcload; -- cpu_pcload
349 isig(8) := DM_STAT_SE.vstart; -- cpu_vstart
350 isig(9) := EI_ACKM_L; -- cpu_irupt (not counting PIRQ!)
351
352 isig(10) := DM_STAT_CA.rd; -- ca_rd
353 isig(11) := DM_STAT_CA.wr; -- ca_wr
354 isig(12) := DM_STAT_CA.rdhit; -- ca_rdhit
355 isig(13) := DM_STAT_CA.wrhit; -- ca_wrhit
356 isig(14) := DM_STAT_CA.rdmem; -- ca_rdmem
357 isig(15) := DM_STAT_CA.wrmem; -- ca_wrmem
358 isig(16) := DM_STAT_CA.rdwait; -- ca_rdwait
359 isig(17) := DM_STAT_CA.wrwait; -- ca_wrwait
360
361 if DM_STAT_VM.ibmreq.aval='1' then
362 if DM_STAT_VM. ibsres.busy='0' then
363 isig(18) := DM_STAT_VM.ibmreq.re; -- ib_rd
364 isig(19) := DM_STAT_VM.ibmreq.we; -- ib_wr
365 else
366 isig(20) := DM_STAT_VM.ibmreq.re or DM_STAT_VM.ibmreq.we; -- ib_busy
367 end if;
368 end if;
369
370 -- a hack too, for 1 core systems is addr(15)='0' when CPU addressed
371 if RB_MREQ.aval='1' and RB_MREQ.addr(15)='0' then
372 if RB_SRES_L.busy='0' then
373 isig(21) := RB_MREQ.re; -- rb_rd
374 isig(22) := RB_MREQ.we; -- rb_wr
375 else
376 isig(23) := RB_MREQ.re or RB_MREQ.we; -- rb_busy
377 end if;
378
379 end if;
380
381 isig(24) := PERFEXT(0); -- ext_rdrhit
382 isig(25) := PERFEXT(1); -- ext_wrrhit
383 isig(26) := PERFEXT(2); -- ext_wrflush
384 isig(27) := PERFEXT(3); -- ext_rlrxact
385 isig(28) := PERFEXT(4); -- ext_rlrxback
386 isig(29) := PERFEXT(5); -- ext_rltxact
387 isig(30) := PERFEXT(6); -- ext_rltxback
388 isig(31) := PERFEXT(7); -- ext_usec
389
390 PERFSIG <= isig;
391 end process proc_sig;
392
393
394 I0: pdp11_dmpcnt
395 generic map (
396 RB_ADDR => rbaddr_dmpcnt_off, -- rbus address
397 VERS => slv(to_unsigned(1, 8)), -- counter layout version
398 -- 33222222222211111111110000000000
399 -- 10987654321098765432109876543210
400 CENA => "11111111111111111111111111111111") -- counter enables
401 port map (
402 CLK => CLK,
403 RESET => RESET_SYS,
404 RB_MREQ => RB_MREQ,
407 );
408 end generate DMPCNT;
409
410 RB_SRES_DMOR : rb_sres_or_4
411 port map (
417 );
418
419 RB_SRES_OR : rb_sres_or_2
420 port map (
424 );
425
426 RB_SRES <= RB_SRES_L; -- setup output signals
428 GRESET <= GRESET_L;
429 CRESET <= CRESET_L;
430 BRESET <= BRESET_L;
433 DM_STAT_EXP.dp_psw <= DM_STAT_DP.psw;
434 DM_STAT_EXP.dp_pc <= DM_STAT_DP.pc;
435 DM_STAT_EXP.dp_dsrc <= DM_STAT_DP.dsrc;
436 DM_STAT_EXP.se_idec <= DM_STAT_SE.idec;
437 DM_STAT_EXP.se_itimer <= DM_STAT_SE.itimer;
438
439-- synthesis translate_off
440
441 TMU : pdp11_tmu_sb
442 generic map (
443 ENAPIN => sbcntl_sbf_tmu)
444 port map (
445 CLK => CLK,
451 );
452-- synthesis translate_on
453
454end syn;
in IB_SRES_2 ib_sres_type := ib_sres_init
in IB_SRES_3 ib_sres_type := ib_sres_init
out IB_SRES_OR ib_sres_type
in IB_SRES_4 ib_sres_type := ib_sres_init
in IB_SRES_1 ib_sres_type
in RESET slbit
Definition: ibd_ibmon.vhd:95
in IB_SRES_SUM ib_sres_type
Definition: ibd_ibmon.vhd:99
AWIDTH natural := 9
Definition: ibd_ibmon.vhd:92
in CLK slbit
Definition: ibd_ibmon.vhd:94
in IB_MREQ ib_mreq_type
Definition: ibd_ibmon.vhd:96
out IB_SRES ib_sres_type
Definition: ibd_ibmon.vhd:97
IB_ADDR slv16 := slv( to_unsigned( 8#160000#, 16) )
Definition: ibd_ibmon.vhd:91
in RESET slbit
Definition: ibd_ibtst.vhd:62
in CLK slbit
Definition: ibd_ibtst.vhd:61
in IB_MREQ ib_mreq_type
Definition: ibd_ibtst.vhd:63
out IB_SRES ib_sres_type
Definition: ibd_ibtst.vhd:65
IB_ADDR slv16 := slv( to_unsigned( 8#170000#, 16) )
Definition: ibd_ibtst.vhd:59
Definition: iblib.vhd:33
in MEM_BUSY slbit
Definition: pdp11_cache.vhd:57
out MEM_DI slv32
Definition: pdp11_cache.vhd:61
in EM_MREQ em_mreq_type
Definition: pdp11_cache.vhd:52
out DM_STAT_CA dm_stat_ca_type
Definition: pdp11_cache.vhd:64
out MEM_BE slv4
Definition: pdp11_cache.vhd:60
in GRESET slbit
Definition: pdp11_cache.vhd:51
in CLK slbit
Definition: pdp11_cache.vhd:50
out MEM_REQ slbit
Definition: pdp11_cache.vhd:55
in MEM_ACK_R slbit
Definition: pdp11_cache.vhd:58
out MEM_ADDR slv20
Definition: pdp11_cache.vhd:59
in MEM_DO slv32
Definition: pdp11_cache.vhd:62
out MEM_WE slbit
Definition: pdp11_cache.vhd:56
TWIDTH positive := 9
Definition: pdp11_cache.vhd:48
in FMISS slbit
Definition: pdp11_cache.vhd:54
out EM_SRES em_sres_type
Definition: pdp11_cache.vhd:53
in CP_STAT cp_stat_type
out CP_CNTL cp_cntl_type
in RB_MREQ rb_mreq_type
out CP_ADDR cp_addr_type
RB_ADDR_CORE slv16 := rbaddr_cpu0_core
RB_ADDR_IBUS slv16 := rbaddr_cpu0_ibus
out RB_SRES rb_sres_type
in RESET slbit
Definition: pdp11_core.vhd:65
in IB_SRES_M ib_sres_type
Definition: pdp11_core.vhd:82
out DM_STAT_DP dm_stat_dp_type
Definition: pdp11_core.vhd:84
in CP_ADDR cp_addr_type
Definition: pdp11_core.vhd:67
out EI_ACKM slbit
Definition: pdp11_core.vhd:76
out DM_STAT_CO dm_stat_co_type
Definition: pdp11_core.vhd:87
in CLK slbit
Definition: pdp11_core.vhd:64
in EM_SRES em_sres_type
Definition: pdp11_core.vhd:78
out CP_DOUT slv16
Definition: pdp11_core.vhd:70
out IB_MREQ_M ib_mreq_type
Definition: pdp11_core.vhd:81
out CRESET slbit
Definition: pdp11_core.vhd:79
in CP_DIN slv16
Definition: pdp11_core.vhd:68
in CP_CNTL cp_cntl_type
Definition: pdp11_core.vhd:66
in EI_VECT slv9_2
Definition: pdp11_core.vhd:75
in EI_PRI slv3
Definition: pdp11_core.vhd:74
out CP_STAT cp_stat_type
Definition: pdp11_core.vhd:69
out DM_STAT_VM dm_stat_vm_type
Definition: pdp11_core.vhd:85
out DM_STAT_SE dm_stat_se_type
Definition: pdp11_core.vhd:83
in ESUSP_I slbit
Definition: pdp11_core.vhd:72
out ESUSP_O slbit
Definition: pdp11_core.vhd:71
out EM_MREQ em_mreq_type
Definition: pdp11_core.vhd:77
out BRESET slbit
Definition: pdp11_core.vhd:80
in HBPT slbit
Definition: pdp11_core.vhd:73
in RESET slbit
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
RB_ADDR slv16 := rbaddr_dmcmon_off
AWIDTH natural := 8
in DM_STAT_SE dm_stat_se_type
in CLK slbit
in RB_MREQ rb_mreq_type
in DM_STAT_VM dm_stat_vm_type
SNUM boolean := false
out RB_SRES rb_sres_type
in RESET slbit
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
in DM_STAT_SE dm_stat_se_type
in CLK slbit
RB_ADDR slv16 := rbaddr_dmhbpt_off
in RB_MREQ rb_mreq_type
in DM_STAT_VM dm_stat_vm_type
out HBPT slbit
out RB_SRES rb_sres_type
NUNIT natural := 2
in RESET slbit
CENA slv32 :=( others => '1')
VERS slv8 := slv( to_unsigned( 1, 8) )
in CLK slbit
in RB_MREQ rb_mreq_type
RB_ADDR slv16 := rbaddr_dmpcnt_off
out RB_SRES rb_sres_type
in PERFSIG slv32
in RESET slbit
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
in DM_STAT_SE dm_stat_se_type
in CLK slbit
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
RB_ADDR slv16 := rbaddr_dmscnt_off
in HM_ENA slbit
Definition: pdp11_mem70.vhd:38
in CLK slbit
Definition: pdp11_mem70.vhd:36
in HM_VAL slbit
Definition: pdp11_mem70.vhd:39
in CRESET slbit
Definition: pdp11_mem70.vhd:37
in IB_MREQ ib_mreq_type
Definition: pdp11_mem70.vhd:41
out CACHE_FMISS slbit
Definition: pdp11_mem70.vhd:40
out IB_SRES ib_sres_type
Definition: pdp11_mem70.vhd:43
rb_sres_type := rb_sres_init RB_SRES_DMCMON
Definition: pdp11_sys70.vhd:97
dm_stat_se_type := dm_stat_se_init DM_STAT_SE
slbit := '0' RESET_SYS
slv32 :=( others => '0') PERFSIG
rb_sres_type := rb_sres_init RB_SRES_DMPCNT
Definition: pdp11_sys70.vhd:95
dm_stat_dp_type := dm_stat_dp_init DM_STAT_DP
dm_stat_vm_type := dm_stat_vm_init DM_STAT_VM
slv16 := x"4000" rbaddr_ibus0
rb_sres_type := rb_sres_init RB_SRES_DMHBPT
Definition: pdp11_sys70.vhd:96
slv16 :=( others => '0') CP_DOUT
slv16 := x"0000" rbaddr_core0
slbit := '0' GRESET_L
em_sres_type := em_sres_init EM_SRES
slbit := '0' BRESET_L
slv16 :=( others => '0') CP_DIN
cp_stat_type := cp_stat_init CP_STAT_L
dm_stat_co_type := dm_stat_co_init DM_STAT_CO
slbit := '0' HBPT
ib_sres_type := ib_sres_init IB_SRES_IBTST
rb_sres_type := rb_sres_init RB_SRES_DMSCNT
Definition: pdp11_sys70.vhd:94
rb_sres_type := rb_sres_init RB_SRES_L
Definition: pdp11_sys70.vhd:99
rb_sres_type := rb_sres_init RB_SRES_CORE
Definition: pdp11_sys70.vhd:93
ib_mreq_type := ib_mreq_init IB_MREQ_M
slbit := '0' RESET_IBTST
ib_sres_type := ib_sres_init IB_SRES_IBMON
cp_addr_type := cp_addr_init CP_ADDR
ib_sres_type := ib_sres_init IB_SRES_M
slbit := '0' CACHE_FMISS
slbit := '0' HM_ENA
slbit := '0' MEM70_FMISS
cp_cntl_type := cp_cntl_init CP_CNTL
em_mreq_type := em_mreq_init EM_MREQ
rb_sres_type := rb_sres_init RB_SRES_DM
Definition: pdp11_sys70.vhd:98
slbit := '0' CRESET_L
dm_stat_ca_type := dm_stat_ca_init DM_STAT_CA
ib_sres_type := ib_sres_init IB_SRES_MEM70
slbit := '0' EI_ACKM_L
in MEM_BUSY slbit
Definition: pdp11_sys70.vhd:81
out RB_LAM_CPU slbit
Definition: pdp11_sys70.vhd:68
out MEM_DI slv32
Definition: pdp11_sys70.vhd:85
in RESET slbit
Definition: pdp11_sys70.vhd:64
out GRESET slbit
Definition: pdp11_sys70.vhd:69
in PERFEXT slv8
Definition: pdp11_sys70.vhd:76
out EI_ACKM slbit
Definition: pdp11_sys70.vhd:75
out MEM_BE slv4
Definition: pdp11_sys70.vhd:84
out RB_STAT slv4
Definition: pdp11_sys70.vhd:67
in CLK slbit
Definition: pdp11_sys70.vhd:63
out MEM_REQ slbit
Definition: pdp11_sys70.vhd:79
in RB_MREQ rb_mreq_type
Definition: pdp11_sys70.vhd:65
out IB_MREQ ib_mreq_type
Definition: pdp11_sys70.vhd:77
out DM_STAT_EXP dm_stat_exp_type
Definition: pdp11_sys70.vhd:88
out CRESET slbit
Definition: pdp11_sys70.vhd:70
in EI_VECT slv9_2
Definition: pdp11_sys70.vhd:74
in EI_PRI slv3
Definition: pdp11_sys70.vhd:73
in MEM_ACK_R slbit
Definition: pdp11_sys70.vhd:82
out CP_STAT cp_stat_type
Definition: pdp11_sys70.vhd:72
out MEM_ADDR slv20
Definition: pdp11_sys70.vhd:83
out RB_SRES rb_sres_type
Definition: pdp11_sys70.vhd:66
in MEM_DO slv32
Definition: pdp11_sys70.vhd:86
out MEM_WE slbit
Definition: pdp11_sys70.vhd:80
in IB_SRES ib_sres_type
Definition: pdp11_sys70.vhd:78
out BRESET slbit
Definition: pdp11_sys70.vhd:71
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
in DM_STAT_SE dm_stat_se_type
in CLK slbit
in DM_STAT_VM dm_stat_vm_type
in DM_STAT_CA dm_stat_ca_type
ENAPIN integer := sbcntl_sbf_tmu
Definition: pdp11.vhd:123
in RB_SRES_2 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
Definition: rblib.vhd:32
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31