w11 - vhd 0.794
W11 CPU core and support modules
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fx2rlinklib.vhd
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1-- $Id: fx2rlinklib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: fx2rlinklib
7-- Description: Definitions for rlink + fx2 interface combos
8--
9-- Dependencies: -
10-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.35
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2019-06-02 1159 1.2.1 use rbaddr_ constants
15-- 2015-04-11 666 1.2 rlink_sp1c_fx2: drop ENAESC
16-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
17-- 2013-04-20 509 1.0 Initial version
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22use ieee.numeric_std.all;
23
24use work.slvtypes.all;
25use work.rblib.all;
26use work.rbdlib.all;
27use work.rlinklib.all;
28use work.serportlib.all;
29use work.fx2lib.all;
30
31package fx2rlinklib is
32
33--
34-- core + fx2 interface combo
35--
36
37component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
38 generic (
39 BTOWIDTH : positive := 5; -- rbus timeout counter width
40 RTAWIDTH : positive := 12; -- retransmit buffer address width
41 SYSID : slv32 := (others=>'0'); -- rlink system id
42 IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
43 OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
44 PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
45 CCWIDTH : positive := 5; -- fx2 chunk counter width
46 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
47 ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
48 ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
49 CDWIDTH : positive := 13; -- clk divider width
50 CDINIT : natural := 15; -- clk divider initial/reset setting
51 RBMON_AWIDTH : natural := 0; -- rbmon: buffer size (0=none)
52 RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
53 port (
54 CLK : in slbit; -- clock
55 CE_USEC : in slbit; -- 1 usec clock enable
56 CE_MSEC : in slbit; -- 1 msec clock enable
57 CE_INT : in slbit := '0'; -- rri ato time unit clock enable
58 RESET : in slbit; -- reset
59 ENAXON : in slbit; -- enable xon/xoff handling
60 ENAFX2 : in slbit; -- enable fx2 usage
61 RXSD : in slbit; -- receive serial data (board view)
62 TXSD : out slbit; -- transmit serial data (board view)
63 CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
64 RTS_N : out slbit; -- request to send (act.low, board view)
65 RB_MREQ : out rb_mreq_type; -- rbus: request
66 RB_SRES : in rb_sres_type; -- rbus: response
67 RB_LAM : in slv16; -- rbus: look at me
68 RB_STAT : in slv4; -- rbus: status flags
69 RL_MONI : out rl_moni_type; -- rlink_core: monitor port
70 RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
71 SER_MONI : out serport_moni_type; -- ser: monitor port
72 FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
73 I_FX2_IFCLK : in slbit; -- fx2: interface clock
74 O_FX2_FIFO : out slv2; -- fx2: fifo address
75 I_FX2_FLAG : in slv4; -- fx2: fifo flags
76 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
77 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
78 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
79 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
80 IO_FX2_DATA : inout slv8 -- fx2: data lines
81 );
82end component;
83
84component ioleds_sp1c_fx2 -- io activity leds for rlink_sp1c_fx2
85 port (
86 CLK : in slbit; -- clock
87 CE_USEC : in slbit; -- 1 usec clock enable
88 RESET : in slbit; -- reset
89 ENAFX2 : in slbit; -- enable fx2 usage
90 RB_SRES : in rb_sres_type; -- rbus: response
91 RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
92 SER_MONI : in serport_moni_type; -- ser: monitor port
93 IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
94 );
95end component;
96
97end package fx2rlinklib;
in SER_MONI serport_moni_type
in RLB_MONI rlb_moni_type
in RB_SRES rb_sres_type
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34