w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
rlink_core.vhd
Go to the documentation of this file.
1-- $Id: rlink_core.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rlink_core - syn
7-- Description: rlink core with 9bit interface (with rlmon+rbmon)
8--
9-- Dependencies: memlib/ram_2swsr_rfirst_gen
10-- memlib/fifo_1c_dram
11-- comlib/crc16
12-- rb_sel
13-- rb_sres_or_2
14-- rlink_mon_sb [sim only]
15-- rbus/rb_mon_sb [sim only]
16--
17-- Test bench: tb/tb_rlink_direct
18-- tb/tb_rlink_serport
19-- tb/tb_rlink_tba_ttcombo
20--
21-- Target Devices: generic
22-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.1; ghdl 0.18-0.34
23--
24-- Synthesized (xst):
25-- Date Rev ise Target flop lutl lutm slic t peri
26-- 2017-05-01 892 14.7 131013 xc6slx16-2 298 709 20 226 s 7.3
27-- 2016-08-21 799 14.7 131013 xc6slx16-2 297 717 20 227 s 7.2 ?incr?
28-- 2015-12-26 718 14.7 131013 xc6slx16-2 312 460 16 150 s 7.0 ver 4.1
29-- 2014-12-20 614 14.7 131013 xc6slx16-2 310 453 16 146 s 6.8 ver 4.0
30-- 2014-08-13 581 14.7 131013 xc6slx16-2 160 230 0 73 s 6.0 ver 3.0
31-- 2014-08-13 581 14.7 131013 xc3s1000-4 160 358 0 221 s 8.9 ver 3.0
32--
33-- Revision History:
34-- Date Rev Version Comment
35-- 2017-05-01 892 4.2 BUGFIX: correct re-transmit after nak aborts
36-- 2016-08-18 799 4.1.3 remove 'assert false' from report statements
37-- 2016-05-22 767 4.1.2 don't init N_REGS (vivado fix for fsm inference)
38-- 2015-12-26 718 4.1.1 add proc_sres: strip 'x' from RB_SRES.dout
39-- 2014-12-21 617 4.1 use stat(_rbf_rbtout) to signal rbus timeout
40-- 2014-12-20 614 4.0 largely rewritten; 2 FSMs; v3 protocol; 4 bit STAT
41-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add s_rxaddrl state
42-- 2011-11-19 427 3.1.3 now numeric_std clean
43-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
44-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
45-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now;
46-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
47-- ioerr->rberr; '111' cmd now aborts via s_txnak and
48-- sets cerr flag; set [cd]err on eop/nak aborts;
49-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now
50-- aval,re,we; add new states: s_rstart, s_wstart
51-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
52-- now nak on reserved cmd 111; use do_comma_abort();
53-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
54-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
55-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
56-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
57-- drop RP_IINT signal from interfaces
58-- 2010-04-03 274 2.1 add CP_FLUSH output
59-- 2009-07-12 233 2.0.1 remove snoopers
60-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
61-- 2008-03-02 121 1.1.1 comment out snoopers
62-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
63-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
64-- 2007-09-15 82 1.0 Initial version, fully functional
65-- 2007-06-17 58 0.5 First preliminary version
66------------------------------------------------------------------------------
67-- 7 supported commands:
68-- nak aborts to _txnak are indicated as [nak:<nakcode>]
69-- commands to rbus engine are indicated as [bcmd:<bfunc>]
70--
71-- 000 read reg (rreg):
72-- rx: cmd al ah ccrcl ccrch
73-- tx: cmd dl dh stat crcl crch
74-- seq: _rxcmd _rxaddrl _rxaddrh
75-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
76-- _rstart[bcmd:rblk] {_txdat}*
77-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
78--
79-- 001 read blk (rblk):
80-- rx: cmd al ah cl ch ccrcl ccrch
81-- tx: cmd cnt dl dh ... dcl dch stat crcl crch
82-- seq: _rxcmd _rxaddrl _rxaddrh _rxcntl _rxcnth
83-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
84-- _txcntl _txcnth _rstart[bcmd:rblk] {_txdat}* _txdcntl _txdcnth
85-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
86--
87-- 010 write reg (wreg):
88-- rx: cmd al ah dl dh ccrcl ccrch
89-- tx: cmd stat crcl crch
90-- seq: _rxcmd _rxaddrl _rxaddrh _rxdatl _rxdath
91-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
92-- _txcmd[bcmd:wblk] _wwait0
93-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
94--
95-- 011 write blk (wblk):
96-- rx: cmd al ah cnt ccrcl ccrch dl dh ... dcrcl dcrch
97-- tx: cmd dcl dch stat crcl crch
98-- seq: _rxcmd _rxaddrl _rxaddrh _rxcntl _rxcnth
99-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
100-- _wblk {_rxwblk}* _rxdcrc[nak:dcrc,rtwblk]
101-- _wblk0 _wblk1 _wblk2[bcmd:wblk] {_wblkl _wblkh}*
102-- _wwait0 _wwait1 _txdcntl _txdcnth
103-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
104--
105-- 100 list abort (labo):
106-- rx: cmd ccrcl ccrch
107-- tx: cmd babo stat crcl crch
108-- seq: _rxcmd
109-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
110-- _txlabo
111-- _txstat_txcrcl[nak:rtovfl] -> _txcrch -> [_rxcmd|_rxeop]
112--
113-- 101 read attn (attn):
114-- rx: cmd ccrcl ccrch
115-- tx: cmd dl dh stat crcl crch
116-- seq: _rxcmd
117-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
118-- _attn _txcntl _txcnth
119-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
120--
121-- 110 write init (init):
122-- rx: cmd al ah dl dh ccrcl ccrch
123-- tx: cmd stat crcl crch
124-- seq: _rxcmd _rxaddrl _rxaddrh _rxdatl _rxdath
125-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd[bcmd:init]
126-- _txstat _txcrc[nak:rtovfl] -> _rxcmd
127--
128-- 111 is currently not a legal command and causes a nak
129-- seq: _txnak
130--
131-- The different rbus cycle types are encoded as:
132--
133-- init aval re we
134-- 0 0 0 0 idle
135-- 0 1 1 0 read
136-- 0 1 0 1 write
137-- 1 0 0 0 init
138-- 0 0 1 0 not allowed
139-- 0 0 0 1 not allowed
140-- 1 0 0 1 not allowed
141-- 1 0 1 0 not allowed
142-- * * 1 1 not allowed
143-- 1 1 * * not allowed
144--
145
146library ieee;
147use ieee.std_logic_1164.all;
148use ieee.numeric_std.all;
149
150use work.slvtypes.all;
151use work.memlib.all;
152use work.comlib.all;
153use work.rblib.all;
154use work.rlinklib.all;
155
156entity rlink_core is -- rlink core with 9bit interface
157 generic (
158 BTOWIDTH : positive := 5; -- rbus timeout counter width
159 RTAWIDTH : positive := 12; -- retransmit buffer address width
160 SYSID : slv32 := (others=>'0'); -- rlink system id
161 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
162 ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
163 port (
164 CLK : in slbit; -- clock
165 CE_INT : in slbit := '0'; -- rri ato time unit clock enable
166 RESET : in slbit; -- reset
167 RL_DI : in slv9; -- rlink 9b: data in
168 RL_ENA : in slbit; -- rlink 9b: data enable
169 RL_BUSY : out slbit; -- rlink 9b: data busy
170 RL_DO : out slv9; -- rlink 9b: data out
171 RL_VAL : out slbit; -- rlink 9b: data valid
172 RL_HOLD : in slbit; -- rlink 9b: data hold
173 RL_MONI : out rl_moni_type; -- rlink: monitor port
174 RB_MREQ : out rb_mreq_type; -- rbus: request
175 RB_SRES : in rb_sres_type; -- rbus: response
176 RB_LAM : in slv16; -- rbus: look at me
177 RB_STAT : in slv4 -- rbus: status flags
178 );
179
180 attribute fsm_encoding : string;
181 attribute fsm_encoding of rlink_core : entity is "one-hot";
182
183end entity rlink_core;
184
185architecture syn of rlink_core is
186 -- core config registers (top 4 in rbus space)
187 constant rbaddr : slv16 := x"fffc"; -- fffc/4: 1111 1111 1111 11xx
188 constant rbaddr_cntl : slv2 := "11"; -- cntl address offset
189 constant rbaddr_stat : slv2 := "10"; -- stat address offset
190 constant rbaddr_id1 : slv2 := "01"; -- id1 address offset
191 constant rbaddr_id0 : slv2 := "00"; -- id0 address offset
192
193 constant d_f_cflag : integer := 8; -- d9: comma flag
194 subtype d_f_ctyp is integer range 2 downto 0; -- d9: comma type
195 subtype d_f_data is integer range 7 downto 0; -- d9: data field
196
197 subtype f_byte1 is integer range 15 downto 8;
198 subtype f_byte0 is integer range 7 downto 0;
199
200 constant cntl_rbf_anena : integer := 15; -- anena flag
201 constant cntl_rbf_atoena : integer := 14; -- atoena flag
202 subtype cntl_rbf_atoval is integer range 7 downto 0; -- atoval value
203 subtype stat_rbf_lcmd is integer range 15 downto 8; -- lcmd
204 constant stat_rbf_babo : integer := 7; -- block abort flag
205 constant stat_rbf_arpend : integer := 6; -- attn read pend
206 subtype stat_rbf_rbsize is integer range 2 downto 0; -- rbuf size
207
208 -- following 4 constants can derived from c_rlink_dat_sop,...
209 -- defined directly here to work around a ghdl bug
210 constant c_sop : slv3 := "000";
211 constant c_eop : slv3 := "001";
212 constant c_nak : slv3 := "010";
213 constant c_attn : slv3 := "011";
214
215 constant c_bcmd_stat : slv2 := "00";
216 constant c_bcmd_init : slv2 := "01";
217 constant c_bcmd_rblk : slv2 := "10";
218 constant c_bcmd_wblk : slv2 := "11";
219
220 constant cntawidth : positive := RTAWIDTH-1; -- cnt is word count
221 subtype cnt_f_dat is integer range cntawidth-1 downto 0; -- cnt data
222
223 -- link FSM states and state vector ----------------------------------------
224 type lstate_type is (
225 sl_idle, -- sl_idle: wait for sop
226 sl_txanot, -- sl_txanot: send attn notify
227 sl_txsop, -- sl_txsop: send sop
228 sl_txnak, -- sl_txnak: send nak
229 sl_txnakcode, -- sl_txnakcode: send nakcode
230 sl_txrtbuf, -- sl_txrtbuf: send rtbuf
231 sl_txeop, -- sl_txeop: send eop
232 sl_rxeop, -- sl_rxeop: wait for eop
233 sl_rxcmd, -- sl_rxcmd: wait for cmd
234 sl_rxaddrl, -- sl_rxaddrl: wait for addr low
235 sl_rxaddrh, -- sl_rxaddrh: wait for addr high
236 sl_rxdatl, -- sl_rxdatl: wait for data low
237 sl_rxdath, -- sl_rxdath: wait for data high
238 sl_rxcntl, -- sl_rxcntl: wait for count low
239 sl_rxcnth, -- sl_rxcnth: wait for count low
240 sl_rxccrcl, -- sl_rxccrcl: wait for command crc low
241 sl_rxccrch, -- sl_rxccrcl: wait for command crc high
242 sl_txcmd, -- sl_txcmd: send cmd
243 sl_txcntl, -- sl_txcntl: send cnt lsb
244 sl_txcnth, -- sl_txcnth: send cnt msb
245 sl_rstart, -- sl_rstart: start rreg or rblk
246 sl_txdat, -- sl_txdat: send data
247 sl_wblk, -- sl_wblk: setup rx wblk data
248 sl_rxwblk, -- sl_rxwblk: wait for wblk data
249 sl_rxdcrcl, -- sl_rxdcrcl: wait for data crc low
250 sl_rxdcrch, -- sl_rxdcrch: wait for data crc high
251 sl_wblk0, -- sl_wblk0: start wblk pipe
252 sl_wblk1, -- sl_wblk1: start wblk data lsb
253 sl_wblk2, -- sl_wblk2: start wblk data msb
254 sl_wblkl, -- sl_wblkl: wblk data lsb
255 sl_wblkh, -- sl_wblkh: wblk data msb
256 sl_wwait0, -- sl_wwait0: wait for wdone
257 sl_wwait1, -- sl_wwait1: wait for dcnt
258 sl_txdcntl, -- sl_txdcntl: send dcnt lsb
259 sl_txdcnth, -- sl_txdcnth: send dcnt lsb
260 sl_txlabo, -- sl_txlabo: send labo flag
261 sl_attn, -- sl_attn: handle attention flags
262 sl_txstat, -- sl_txstat: send status
263 sl_txcrcl, -- sl_txcrcl: send crc low
264 sl_txcrch -- sl_txcrch: send crc high
265 );
266
267 type lregs_type is record
268 state : lstate_type; -- state
269 rcmd : slv8; -- received command
270 lcmd : slv8; -- last command
271 addr : slv16; -- rbus register address
272 din : slv16; -- rbus input data
273 cnt : slv16; -- block transfer count
274 bcnt : slv(RTAWIDTH-1 downto 0); -- blk counter (byte and word)
275 attn : slv16; -- attn mask
276 anreq : slbit; -- attn notify request
277 anact : slbit; -- attn notify active
278 arpend : slbit; -- attn read pending
279 atocnt : slv8; -- attn timeout counter
280 babo : slbit; -- last blk aborted
281 nakdone : slbit; -- nak done
282 nakcode : slv3; -- nak code
283 cmdseen : slbit; -- 1st command seen
284 doretra : slbit; -- do a retransmit
285 dinl : slv8; -- din lsb for wblk pipeline
286 rtaddra : slv(RTAWIDTH-1 downto 0); -- rtbuf port a addr (write pointer)
287 rtaddra_red : slbit; -- rtaddra red (at max)
288 rtaddra_bad : slbit; -- rtaddra bad (inc beyond max)
289 rtaddra_zero : slbit; -- rtaddra was 0 in last cycle
290 rtaddrb : slv(RTAWIDTH-1 downto 0); -- rtbuf port b addr (aux pointer)
291 rtaddrb_red : slbit; -- rtaddrb red (at max)
292 rtaddrb_bad : slbit; -- rtaddrb bad (inc beyond max)
293 moneop : slbit; -- rl_moni: eop send pulse
294 monattn : slbit; -- rl_moni: attn send pulse
295 end record lregs_type;
296
297 constant bcnt_zero : slv(RTAWIDTH-1 downto 0) := (others=>'0');
298 constant rtaddr_zero : slv(RTAWIDTH-1 downto 0) := (others=>'0');
299 constant rtaddr_tred : slv(RTAWIDTH-1 downto 0) := (0=>'0', others=>'1');
300
301 constant lregs_init : lregs_type := (
302 sl_idle, -- state
303 (others=>'0'), -- rcmd
304 (others=>'1'), -- lcmd
305 (others=>'0'), -- addr
306 (others=>'0'), -- din
307 (others=>'0'), -- cnt
308 bcnt_zero, -- bcnt
309 (others=>'0'), -- attn
310 '0','0','0', -- anreq,anact,arpend
311 (others=>'0'), -- atocnt
312 '0', -- babo
313 '0', -- nakdone
314 (others=>'0'), -- nakcode
315 '0','0', -- cmdseen,doretra
316 (others=>'0'), -- dinl
317 rtaddr_zero, -- rtaddra
318 '0','0','0', -- rtaddra_(red|bad|zero)
319 rtaddr_zero, -- rtaddrb
320 '0','0', -- rtaddrb_(red,bad)
321 '0','0' -- moneop,monattn
322 );
323
324 -- bus FSM states and state vector -----------------------------------------
325 type bstate_type is (
326 sb_idle, -- sb_idle: wait for cmd
327 sb_rstart, -- sb_rstart: start rblk
328 sb_rreg0, -- sb_rreg0: rbus read cycle
329 sb_rreg1, -- sb_rreg1: send read data
330 sb_rwait, -- sb_rwait: wait for fifo
331 sb_rend, -- sb_rend: send last read data
332 sb_rabo0, -- sb_rabo0: rblk abort, lsb data
333 sb_rabo1, -- sb_rabo1: rblk abort, msb data
334 sb_wstart, -- sb_wstart: start wblk
335 sb_wreg0, -- sb_wreg0: rbus write cycle
336 sb_wreg1, -- sb_wreg1: wait write data
337 sb_wabo0, -- sb_wabo0: wblk abort, drop data
338 sb_wabo1 -- sb_wabo1: wblk abort, wait
339 );
340
341 type bregs_type is record
342 state : bstate_type; -- state
343 rbinit : slbit; -- rbus init signal
344 rbaval : slbit; -- rbus aval signal
345 rbre : slbit; -- rbus re signal
346 rbwe : slbit; -- rbus we signal
347 rbdout : slv16; -- rbus dout
348 rbtout: slbit; -- rbus timeout
349 rbnak: slbit; -- rbus no ack
350 rberr : slbit; -- rbus err bit set
351 blkabo : slbit; -- blk abort
352 cnt : slv(cntawidth-1 downto 0); -- word count for rblk and wblk
353 dcnt : slv(cntawidth-1 downto 0); -- done count for rblk and wblk
354 btocnt : slv(BTOWIDTH-1 downto 0); -- rbus timeout counter
355 dathpend : slbit; -- dat msb pending
356 wfifo : slbit; -- wait for fifo
357 stat : slv4; -- external status flags
358 end record bregs_type;
359
360 constant btocnt_init : slv(BTOWIDTH-1 downto 0) := (others=>'1');
361 constant cnt_zero : slv(cntawidth-1 downto 0) := (others=>'0');
362
363 constant bregs_init : bregs_type := (
364 sb_idle, -- state
365 '0','0','0','0', -- rbinit,rbaval,rbre,rbwe
366 (others=>'0'), -- rbdout
367 '0','0','0', -- rbtout,rbnak,rberr
368 '0', -- blkabo
369 cnt_zero, -- cnt
370 cnt_zero, -- dcnt
371 btocnt_init, -- btocnt
372 '0','0', -- dathpend,wfifo
373 (others=>'0') -- stat
374 );
375
376 -- config state regs --------------------------------------------------------
377 type cregs_type is record
378 anena : slbit; -- attn notification enable flag
379 atoena : slbit; -- attn timeout enable flag
380 atoval : slv8; -- attn timeout value
381 end record cregs_type;
382
383 constant cregs_init : cregs_type := (
384 '0','0', -- anena,atoena
385 (others=>'0') -- atoval
386 );
387
388 signal R_LREGS : lregs_type := lregs_init; -- state registers link FSM
389 signal N_LREGS : lregs_type; -- don't init (vivado fix for fsm infer)
390 signal R_BREGS : bregs_type := bregs_init; -- state registers bus FSM
391 signal N_BREGS : bregs_type; -- don't init (vivado fix for fsm infer)
392 signal R_CREGS : cregs_type := cregs_init; -- state registers config
393 signal N_CREGS : cregs_type := cregs_init; -- next value state regs config
394
395 signal RTBUF_ENB : slbit := '0';
396 signal RTBUF_WEA : slbit := '0';
397 signal RTBUF_WEB : slbit := '0';
398 signal RTBUF_DIA : slv8 := (others=>'0');
399 signal RTBUF_DIB : slv8 := (others=>'0');
400 signal RTBUF_DOB : slv8 := (others=>'0');
401
402 signal DOFIFO_DI : slv8 := (others=>'0');
403 signal DOFIFO_ENA : slbit := '0';
404 signal DOFIFO_DO : slv8 := (others=>'0');
405 signal DOFIFO_VAL : slbit := '0';
406 signal DOFIFO_HOLD : slbit := '0';
407 signal DOFIFO_SIZE : slv6 := (others=>'0');
408
409 signal CRC_RESET : slbit := '0';
410 signal ICRC_ENA : slbit := '0';
411 signal OCRC_ENA : slbit := '0';
412 signal ICRC_OUT : slv16 := (others=>'0');
413 signal OCRC_OUT : slv16 := (others=>'0');
414 signal OCRC_IN : slv8 := (others=>'0');
415
416 signal RBSEL : slbit := '0';
417
418 signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- internal mreq
419 signal RB_SRES_CLEAN : rb_sres_type := rb_sres_init; -- cleaned rb_sres
420 signal RB_SRES_CONF : rb_sres_type := rb_sres_init; -- config sres
421 signal RB_SRES_TOT : rb_sres_type := rb_sres_init; -- total sres
422
423 signal RL_BUSY_L : slbit := '0';
424 signal RL_DO_L : slv9 := (others=>'0');
425 signal RL_VAL_L : slbit := '0';
426
427 signal L2B_GO : slbit := '0';
428 signal L2B_CMD : slv2 := (others=>'0');
429 signal B2L_WDONE : slbit := '0';
430
431begin
432
433 -- allow 11 bit (1 x 18kbit BRAM) to 15 bit (8 x 36 kbit BRAMs)
434 assert RTAWIDTH>=11 and RTAWIDTH<=14
435 report "assert(RTAWIDTH>=11 and RTAWIDTH<=15): unsupported RTAWIDTH"
436 severity failure;
437
438 RTBUF : ram_2swsr_rfirst_gen
439 generic map (
440 AWIDTH => RTAWIDTH,
441 DWIDTH => 8)
442 port map (
443 CLKA => CLK,
444 CLKB => CLK,
445 ENA => RTBUF_WEA, -- port A write only, thus en=we
446 ENB => RTBUF_ENB,
447 WEA => RTBUF_WEA,
448 WEB => RTBUF_WEB,
449 ADDRA => R_LREGS.rtaddra,
450 ADDRB => R_LREGS.rtaddrb,
451 DIA => RTBUF_DIA,
452 DIB => RTBUF_DIB,
453 DOA => open,
454 DOB => RTBUF_DOB
455 );
456
457 DOFIFO : fifo_1c_dram
458 generic map (
459 AWIDTH => 5,
460 DWIDTH => 8)
461 port map (
462 CLK => CLK,
463 RESET => RESET,
464 DI => DOFIFO_DI,
465 ENA => DOFIFO_ENA,
466 BUSY => open,
467 DO => DOFIFO_DO,
468 VAL => DOFIFO_VAL,
469 HOLD => DOFIFO_HOLD,
470 SIZE => DOFIFO_SIZE
471 );
472
473 ICRC : crc16 -- crc generator for input data
474 port map (
475 CLK => CLK,
476 RESET => CRC_RESET,
477 ENA => ICRC_ENA,
478 DI => RL_DI(d_f_data),
479 CRC => ICRC_OUT
480 );
481
482 OCRC : crc16 -- crc generator for output data
483 port map (
484 CLK => CLK,
485 RESET => CRC_RESET,
486 ENA => OCRC_ENA,
487 DI => OCRC_IN,
488 CRC => OCRC_OUT
489 );
490
491 SEL : rb_sel -- rbus address select for config regs
492 generic map (
493 RB_ADDR => rbaddr,
494 SAWIDTH => 2)
495 port map (
496 CLK => CLK,
497 RB_MREQ => RB_MREQ_L,
498 SEL => RBSEL
499 );
500
501 RB_SRES_OR : rb_sres_or_2
502 port map (
503 RB_SRES_1 => RB_SRES_CLEAN,
504 RB_SRES_2 => RB_SRES_CONF,
505 RB_SRES_OR => RB_SRES_TOT
506 );
507
508 proc_sres: process (RB_SRES)
509 variable sres : rb_sres_type := rb_sres_init;
510 variable datax01 : slv16 := (others=>'0');
511 variable data01 : slv16 := (others=>'0');
512 begin
513 sres.ack := to_x01(RB_SRES.ack);
514 sres.busy := to_x01(RB_SRES.busy);
515 sres.err := to_x01(RB_SRES.err);
516 sres.dout := to_x01(RB_SRES.dout);
517
518 if sres.ack = '1' and sres.busy = '0' and is_x(sres.dout) then
519 report "rlink_core: seen 'x' in rb_sres.data"
520 severity warning;
521 sres.dout := (others=>'1');
522 end if;
523
524 RB_SRES_CLEAN <= sres;
525 end process proc_sres;
526
527 proc_regs: process (CLK)
528 begin
529
530 if rising_edge(CLK) then
531 if RESET = '1' then
532 R_LREGS <= lregs_init;
533 R_BREGS <= bregs_init;
534 R_CREGS <= cregs_init;
535 else
536 R_LREGS <= N_LREGS;
537 R_BREGS <= N_BREGS;
538 R_CREGS <= N_CREGS;
539 end if;
540 end if;
541
542 end process proc_regs;
543
544 -- link FSM ================================================================
545
546 proc_lnext: process (R_LREGS, R_CREGS, R_BREGS,
547 CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
548 ICRC_OUT, OCRC_OUT, RTBUF_DOB,
549 DOFIFO_DO, DOFIFO_VAL,
550 B2L_WDONE)
551
552 variable r : lregs_type := lregs_init;
553 variable n : lregs_type := lregs_init;
554
555 variable ival : slbit := '0';
556 variable ibusy : slbit := '0';
557 variable ido : slv9 := (others=>'0');
558 variable crcreset : slbit := '0';
559 variable icrcena : slbit := '0';
560 variable ocrcena : slbit := '0';
561 variable has_attn : slbit := '0';
562 variable idi8 : slv8 := (others=>'0');
563 variable is_comma : slbit := '0';
564 variable comma_typ : slv3 := "000";
565 variable idohold : slbit := '0';
566 variable cnt_iszero : slbit := '0';
567 variable bcnt_load : slbit := '0';
568 variable bcnt_val : slv(RTAWIDTH-1 downto 0) := (others=>'0');
569 variable bcnt_dec : slbit := '0';
570 variable bcnt_end : slbit := '0';
571 variable irtwea : slbit := '0';
572 variable irtreb : slbit := '0';
573 variable irtweb : slbit := '0';
574 variable addra_clear : slbit := '0';
575 variable addrb_load : slbit := '0';
576 variable addrb_sela : slbit := '0';
577 variable ibcmd : slv2 := (others=>'0');
578 variable ibgo : slbit := '0';
579
580 begin
581
582 r := R_LREGS;
583 n := R_LREGS;
584
585 n.moneop := '0'; -- default '0', only set by states
586 n.monattn := '0'; -- "
587
588 ival := '0';
589 ibusy := '1'; -- default is to hold input
590 ido := (others=>'0');
591
592 crcreset := '0';
593 icrcena := '0';
594 ocrcena := '0';
595
596 has_attn := '0';
597
598 is_comma := RL_DI(d_f_cflag); -- get comma marker
599 comma_typ := RL_DI(d_f_ctyp); -- get comma type
600 idi8 := RL_DI(d_f_data); -- get data part of RL_DI
601
602 idohold := '1'; -- default is to hold DOFIFO
603
604 cnt_iszero := '0';
605 if unsigned(r.cnt(cnt_f_dat)) = 0 then
606 cnt_iszero := '1';
607 end if;
608
609 bcnt_load := '0';
610 bcnt_val := r.cnt(cnt_f_dat) & '0'; -- default: 2*cnt (most used)
611 bcnt_dec := '0';
612 bcnt_end := '0';
613 if unsigned(r.bcnt) = 1 then
614 bcnt_end := '1';
615 end if;
616
617 irtwea := '0';
618 irtreb := '0';
619 irtweb := '0';
620 addra_clear := '0';
621 addrb_load := '0';
622 addrb_sela := '1'; -- default: addra (most used)
623
624 ibcmd := (others=>'0');
625 ibgo := '0';
626
627 -- handle attention "LAM's"
628 n.attn := r.attn or RB_LAM;
629
630 -- detect attn notify requests
631 if unsigned(r.attn) /= 0 then -- if any of the attn bits set
632 has_attn := '1';
633 if R_CREGS.anena='1' and r.arpend='0' then -- if attn to be send
634 n.anreq := '1'; -- set notify request flag
635 end if;
636 end if;
637
638 -- handle attn read timeouts
639 -- atocnt is held in reset when no attn read is pending
640 -- counting down in CE_INT cycles till zero
641 -- when zero, an attn notify is requested when atoena is set
642 -- the attn notify flag will reset atocnt to its start value
643 -- --> when atoena='1' this creates a notify every atoval CE_INT periods
644 -- --> when atoena='0' atocnt will count to zero and stay there
645
646 if r.arpend = '0' or r.anreq = '1' then -- if no attn read pending
647 n.atocnt := R_CREGS.atoval; -- keep at start value
648 else -- otherwise
649 if CE_INT = '1' then -- if CE_INT
650 if unsigned(r.atocnt) = 0 then -- alread counted down
651 n.anreq := R_CREGS.atoena; -- request attn notify if enabled
652 else -- not yet down
653 n.atocnt := slv(unsigned(r.atocnt) - 1); -- decrement
654 end if;
655 end if;
656 end if;
657
658 case r.state is
659
660 when sl_idle => -- sl_idle: wait for sop -------------
661 bcnt_val := r.rtaddra; -- used for nak handling
662 addrb_sela := '0';
663 n.anact := '0';
664 n.doretra := '0';
665 crcreset := '1'; -- reset crc generators
666 if r.anreq = '1' then -- if attn notify requested
667 n.anreq := '0'; -- acknowledge request
668 n.arpend := '1'; -- mark attn read pending
669 n.state := sl_txanot; -- next: send attn notify
670 else
671 ibusy := '0'; -- accept input
672 if RL_ENA = '1' then -- if input
673 if is_comma = '1' then -- if comma
674 case comma_typ is
675 when c_sop => -- if sop
676 n.cmdseen := '0'; -- clear cmd seen flag
677 n.state := sl_txsop; -- next: echo it
678 when c_attn => -- if attn
679 n.state := sl_txanot; -- next: send attn notify
680 when c_nak =>
681 addrb_load := '1';
682 bcnt_load := '1';
683 n.doretra := '1';
684 n.state := sl_txsop; -- next: send sop
685 when others => null; -- other commas: silently ignore
686 -- especially: eop is ignored
687 end case;
688 else -- if normal data
689 n.state := sl_idle; -- silently dropped
690 end if;
691 end if;
692 end if;
693
694 when sl_txanot => -- sl_txanot: send attn notify -------
695 n.cnt := r.attn; -- transfer attn to cnt for transmit
696 n.anact := '1'; -- signal attn notify active
697 ido := c_rlink_dat_attn; -- send attn symbol
698 ival := '1';
699 if RL_HOLD = '0' then -- wait for accept
700 n.monattn := '1'; -- signal on rl_moni
701 n.state := sl_txcntl; -- next: send cnt lsb
702 end if;
703
704 when sl_txsop => -- sl_txsop: send sop ----------------
705 ido := c_rlink_dat_sop; -- send sop character
706 ival := '1';
707 if RL_HOLD = '0' then -- wait for accept
708 if r.doretra = '1' then -- if retra request
709 if r.rtaddra_zero = '1' then -- nothing to send
710 if r.nakdone = '0' then -- if no nak active
711 n.state := sl_txeop; -- next: send eop
712 else
713 n.state := sl_txnak; -- next: send nak
714 end if;
715 else -- something to send
716 irtreb := '1'; -- request first byte
717 n.state := sl_txrtbuf; -- next: send rtbuf
718 end if;
719 else -- or normal command
720 n.state := sl_rxcmd; -- next: read first command
721 end if;
722 end if;
723
724 when sl_txnak => -- sl_txnak: send nak ----------------
725 n.nakdone := '1'; -- set nakdone flag
726 ido := c_rlink_dat_nak; -- send nak character
727 ival := '1';
728 if RL_HOLD = '0' then -- wait for accept
729 n.state := sl_txnakcode; -- next: send nakcode
730 end if;
731
732 when sl_txnakcode => -- sl_txnakcode: send nakcode --------
733 ido := '0' & "10" & (not r.nakcode) & r.nakcode;
734 ival := '1';
735 if RL_HOLD = '0' then -- wait for accept
736 if r.doretra = '0' then -- if no nak active
737 n.state := sl_rxeop; -- next: wait for eop
738 else -- else of nak active
739 n.state := sl_txeop; -- next: send eop
740 end if;
741 end if;
742
743 when sl_rxeop => -- sl_rxeop: wait for eop ------------
744 ibusy := '0'; -- accept input
745 if RL_ENA = '1' then
746 if is_comma = '1' and comma_typ = c_eop then -- if eop seen
747 n.state := sl_txeop; -- next: echo eop
748 end if;
749 end if;
750
751 when sl_txrtbuf => -- sl_txrtbuf: send rtbuf ------------
752 ido := '0' & RTBUF_DOB; -- send rtbuf data
753 ival := '1';
754 if RL_HOLD = '0' then -- wait for accept
755 bcnt_dec := '1';
756 if bcnt_end = '0' then -- if not yet done
757 irtreb := '1'; -- request next byte
758 else -- all done
759 if r.nakdone = '0' then -- if no nak active
760 n.state := sl_txeop; -- next: send eop
761 else
762 n.state := sl_txnak; -- next: send nak
763 end if;
764 end if;
765 end if;
766
767 when sl_txeop => -- sl_txeop: send eop ----------------
768 n.state := sl_txeop; -- needed to prevent vivado iSTATE
769 ido := c_rlink_dat_eop; -- send eop character
770 ival := '1';
771 if RL_HOLD = '0' then -- wait for accept
772 n.moneop := '1'; -- signal on rl_moni
773 n.state := sl_idle; -- next: idle state, wait for sop
774 end if;
775
776 when sl_rxcmd => -- sl_rxcmd: wait for cmd ------------
777 ibusy := '0'; -- accept input
778 n.cnt := slv(to_unsigned(1,16)); -- preset cnt=1 (used for rreg)
779 n.rcmd := idi8; -- latch cmd (follow till valid)
780 if RL_ENA = '1' then
781 if is_comma = '1' then -- if comma
782 if comma_typ = c_eop then -- eop seen
783 n.state := sl_txeop; -- next: echo eop
784 else -- any other comma seen
785 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
786 n.state := sl_txnak; -- next: send nak
787 end if;
788 else -- if not comma
789 if r.cmdseen = '0' then -- if first cmd
790 n.nakdone := '0'; -- clear nakdone flag
791 addra_clear := '1'; -- clear rtbuf
792 end if;
793 n.cmdseen := '1'; -- set cmd seen flag
794 icrcena := '1'; -- update input crc
795 case RL_DI(c_rlink_cmd_rbf_code) is
796 when c_rlink_cmd_rreg |
797 c_rlink_cmd_rblk |
798 c_rlink_cmd_wreg |
799 c_rlink_cmd_wblk |
800 c_rlink_cmd_init => -- for commands needing addr(data)
801 n.state := sl_rxaddrl; -- next: read address lsb
802 when c_rlink_cmd_labo |
803 c_rlink_cmd_attn => -- labo and attn commands
804 n.state := sl_rxccrcl; -- next: read command crc low
805 when others =>
806 n.nakcode := c_rlink_nakcode_cmd; -- signal bad cmd
807 n.state := sl_txnak; -- next: send nak
808 end case;
809 end if;
810 end if;
811
812 when sl_rxaddrl => -- sl_rxaddrl: wait for addr lsb -----
813 ibusy := '0'; -- accept input
814 n.addr(f_byte0) := idi8; -- latch addr lsb (follow till valid)
815 if RL_ENA = '1' then
816 if is_comma = '1' then -- if comma
817 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
818 n.state := sl_txnak; -- next: send nak,
819 else
820 icrcena := '1'; -- update input crc
821 n.state := sl_rxaddrh; -- next: read addr msb
822 end if;
823 end if;
824
825 when sl_rxaddrh => -- sl_rxaddrh: wait for addr msb -----
826 ibusy := '0'; -- accept input
827 n.addr(f_byte1) := idi8; -- latch addr msb (follow till valid)
828 if RL_ENA = '1' then
829 if is_comma = '1' then -- if comma
830 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
831 n.state := sl_txnak; -- next: send nak
832 else
833 icrcena := '1'; -- update input crc
834 case r.rcmd(c_rlink_cmd_rbf_code) is
835 when c_rlink_cmd_rreg => -- for rreg command
836 n.state := sl_rxccrcl; -- next: read command crc low
837 when c_rlink_cmd_wreg |
838 c_rlink_cmd_init => -- for wreg, init command
839 n.state := sl_rxdatl; -- next: read data lsb
840 when others => -- for rblk or wblk
841 n.state := sl_rxcntl; -- next: read count lsb
842 end case;
843 end if;
844 end if;
845
846 when sl_rxdatl => -- sl_rxdatl: wait for data low ------
847 ibusy := '0'; -- accept input
848 n.din(f_byte0) := idi8; -- latch data lsb (follow till valid)
849 if RL_ENA = '1' then
850 if is_comma = '1' then -- if comma
851 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
852 n.state := sl_txnak; -- next: send nak
853 else
854 icrcena := '1'; -- update input crc
855 n.state := sl_rxdath; -- next: read data msb
856 end if;
857 end if;
858
859 when sl_rxdath => -- sl_rxdath: wait for data high -----
860 ibusy := '0'; -- accept input
861 n.din(f_byte1) := idi8; -- latch data msb (follow till valid)
862 if RL_ENA = '1' then
863 if is_comma = '1' then -- if comma
864 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
865 n.state := sl_txnak; -- next: send nak
866 else
867 icrcena := '1'; -- update input crc
868 n.state := sl_rxccrcl; -- next: read command crc low
869 end if;
870 end if;
871
872 when sl_rxcntl => -- sl_rxcntl: wait for count lsb -----
873 ibusy := '0'; -- accept input
874 n.cnt(f_byte0) := idi8; -- latch count lsb (follow till valid)
875 if RL_ENA = '1' then
876 if is_comma = '1' then -- if comma
877 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
878 n.state := sl_txnak; -- next: send nak
879 else
880 icrcena := '1'; -- update input crc
881 n.state := sl_rxcnth; -- next: read count msb
882 end if;
883 end if;
884
885 when sl_rxcnth => -- sl_rxcnth: wait for count msb -----
886 ibusy := '0'; -- accept input
887 n.cnt(f_byte1) := idi8; -- latch count lsb (follow till valid)
888 if RL_ENA = '1' then
889 if is_comma = '1' then -- if comma
890 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
891 n.state := sl_txnak; -- next: send nak
892 else
893 icrcena := '1'; -- update input crc
894 if unsigned(idi8(7 downto cntawidth-8)) = 0 then -- if cnt ok
895 n.state := sl_rxccrcl; -- next: read command crc low
896 else
897 n.nakcode := c_rlink_nakcode_cnt; -- signal bad cnt
898 n.state := sl_txnak; -- next: send nak
899 end if;
900 end if;
901 end if;
902
903 when sl_rxccrcl => -- sl_rxccrcl: wait for command crc low
904 ibusy := '0'; -- accept input
905 if RL_ENA = '1' then
906 if is_comma = '1' then -- if comma
907 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
908 n.state := sl_txnak; -- next: send nak
909 else
910 if idi8 /= ICRC_OUT(f_byte0) then -- if crc error (lsb)
911 n.nakcode := c_rlink_nakcode_ccrc; -- signal bad ccrc
912 n.state := sl_txnak; -- next: send nak
913 else -- if crc ok
914 n.state := sl_rxccrch; -- next: wait for command crc high
915 end if;
916 end if;
917 end if;
918
919 when sl_rxccrch => -- sl_rxccrcl: wait for command crc high
920 ibusy := '0'; -- accept input
921 if RL_ENA = '1' then
922 if is_comma = '1' then -- if comma
923 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
924 n.state := sl_txnak; -- next: send nak
925 else
926 if idi8 /= ICRC_OUT(f_byte1) then -- if crc error (msb)
927 n.nakcode := c_rlink_nakcode_ccrc; -- signal bad ccrc
928 n.state := sl_txnak; -- next: send nak
929 else -- if crc ok
930 n.state := sl_txcmd; -- next: echo command
931 end if;
932 end if;
933 end if;
934
935 when sl_txcmd => -- sl_txcmd: send cmd -----------------
936 ido := '0' & r.rcmd; -- send read command
937 ival := '1';
938 if RL_HOLD = '0' then -- wait for accept
939 irtwea := '1';
940 ocrcena := '1'; -- update output crc
941 ibcmd := c_bcmd_stat; -- latch external status bits
942 ibgo := '1';
943
944 case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
945 when c_rlink_cmd_rreg => -- rreg ----------------
946 n.state := sl_rstart; -- next: start rreg
947 when c_rlink_cmd_rblk => -- rblk ----------------
948 n.babo := '0'; -- clear babo flag
949 n.state := sl_txcntl;
950 when c_rlink_cmd_wreg => -- wreg ----------------
951 ibcmd := c_bcmd_wblk;
952 ibgo := '1';
953 n.state := sl_wwait0; -- next: wait for wdone
954 when c_rlink_cmd_wblk => -- wblk ----------------
955 n.babo := '0'; -- clear babo flag
956 if cnt_iszero = '0' then -- if cnt /= 0
957 n.state := sl_wblk; -- next: read wblk data
958 else -- otherwise cnt = 0
959 n.state := sl_rxdcrcl; -- next: wait for dcrc low
960 end if;
961 when c_rlink_cmd_labo => -- labo ----------------
962 n.state := sl_txlabo;
963 when c_rlink_cmd_attn => -- attn ----------------
964 n.state := sl_attn;
965 when c_rlink_cmd_init => -- init ----------------
966 ibcmd := c_bcmd_init;
967 ibgo := '1';
968 n.state := sl_txstat;
969
970 when others => -- '111' ---------------
971 n.nakcode := c_rlink_nakcode_cmd; -- signal bad cmd
972 n.state := sl_txnak; -- send NAK on reserved command
973 end case;
974 end if;
975
976 when sl_txcntl => -- sl_txcntl: send cnt lsb ------------
977 ido := '0' & r.cnt(f_byte0); -- send cnt lsb
978 ival := '1';
979 if RL_HOLD = '0' then -- wait for accept
980 irtwea := not r.anact; -- no rtbuf for attn notify
981 ocrcena := '1'; -- update output crc
982 n.state := sl_txcnth; -- next: send cnt msb
983 end if;
984
985 when sl_txcnth => -- sl_txcnth: send cnt msb ------------
986 ido := '0' & r.cnt(f_byte1); -- send cnt msb
987 ival := '1';
988 if RL_HOLD = '0' then -- wait for accept
989 irtwea := not r.anact; -- no rtbuf for attn notify
990 ocrcena := '1'; -- update output crc
991 if r.anact = '1' then -- if in attn notify
992 n.state := sl_txcrcl; -- next: send crc low
993 elsif r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
994 if cnt_iszero = '0' then -- if cnt /= 0
995 n.state := sl_rstart; -- next: start rblk
996 else -- otherwise cnt = 0
997 n.state := sl_txdcntl; -- next: send dcnt lsb
998 end if;
999 else -- otherwise, must be attn
1000 n.state := sl_txstat; -- next: send stat
1001 end if;
1002 end if;
1003
1004 when sl_rstart => -- sl_rstart: start rreg or rblk -----
1005 ibcmd := c_bcmd_rblk;
1006 ibgo := '1';
1007 bcnt_load := '1';
1008 bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2*cnt
1009 n.state := sl_txdat;
1010
1011 when sl_txdat => -- sl_txdat: send data ---------------
1012 ido := '0' & DOFIFO_DO;
1013 if DOFIFO_VAL = '1' then -- wait for input
1014 ival := '1';
1015 if RL_HOLD = '0' then -- wait for accept
1016 idohold := '0';
1017 irtwea := '1';
1018 ocrcena := '1'; -- update output crc
1019 bcnt_dec := '1';
1020 if bcnt_end = '1' then
1021 if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
1022 n.state := sl_txdcntl;
1023 else
1024 n.state := sl_txstat;
1025 end if;
1026 end if;
1027 end if;
1028 end if;
1029
1030 when sl_wblk => -- sl_wblk: setup rx wblk data -------
1031 addrb_load := '1'; -- must be done here because addra
1032 addrb_sela := '1'; -- is incremented in _txcmd
1033 bcnt_load := '1';
1034 bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2*cnt
1035 n.state := sl_rxwblk;
1036
1037 when sl_rxwblk => -- sl_rxwblk: wait for wblk data -----
1038 ibusy := '0'; -- accept input
1039 if RL_ENA = '1' then
1040 if is_comma = '1' then -- if comma
1041 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
1042 n.state := sl_txnak; -- next: send nak
1043 else
1044 icrcena := '1'; -- update input crc
1045 irtweb := '1'; -- write into rtbuf via b port
1046 bcnt_dec := '1';
1047 if bcnt_end = '1' then -- if all done
1048 n.state := sl_rxdcrcl; -- next: wait for data crc low
1049 end if;
1050 end if;
1051 end if;
1052
1053 when sl_rxdcrcl => -- sl_rxdcrcl: wait for data crc low -
1054 ibusy := '0'; -- accept input
1055 bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2 * cnt
1056 addrb_sela := '1';
1057 if RL_ENA = '1' then
1058 if is_comma = '1' then -- if comma
1059 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
1060 n.state := sl_txnak; -- next: send nak
1061 else
1062 if idi8 /= ICRC_OUT(f_byte0) then -- if crc error lsb
1063 n.nakcode := c_rlink_nakcode_dcrc; -- signal bad dcrc
1064 n.state := sl_txnak; -- next: send nak
1065 else -- if crc ok
1066 n.state := sl_rxdcrch; -- next: wait for data crc high
1067 end if;
1068 end if;
1069 end if;
1070
1071 when sl_rxdcrch => -- sl_rxdcrch: wait for data crc high
1072 ibusy := '0'; -- accept input
1073 bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2 * cnt
1074 addrb_sela := '1';
1075 if RL_ENA = '1' then
1076 if is_comma = '1' then -- if comma
1077 n.nakcode := c_rlink_nakcode_frame; -- signal framing error
1078 n.state := sl_txnak; -- next: send nak
1079 else
1080 if idi8 /= ICRC_OUT(f_byte1) then -- if crc error msb
1081 n.nakcode := c_rlink_nakcode_dcrc; -- signal bad dcrc
1082 n.state := sl_txnak; -- next: send nak
1083 else -- if crc ok
1084 addrb_load := '1';
1085 bcnt_load := '1';
1086 if r.rtaddrb_bad = '0' then -- if rtbuf ok
1087 n.state := sl_wblk0; -- next: start wblk pipe
1088 else -- else rtbuf ovfl
1089 n.nakcode := c_rlink_nakcode_rtwblk; -- signal ovfl in wblk
1090 n.state := sl_txnak; -- next: send nak
1091 end if;
1092 end if;
1093 end if;
1094 end if;
1095
1096 when sl_wblk0 => -- sl_wblk0: start wblk pipe ---------
1097 if cnt_iszero = '0' then -- if cnt /= 0
1098 irtreb := '1'; -- request next byte
1099 n.state := sl_wblk1; -- next: start data lsb
1100 else -- otherwise cnt = 0
1101 n.state := sl_txdcntl; -- next: send dcnt lsb
1102 end if;
1103
1104 when sl_wblk1 => -- sl_wblk1: start wblk data lsb -----
1105 n.dinl := RTBUF_DOB; -- latch data lsb
1106 irtreb := '1'; -- request next byte
1107 bcnt_dec := '1';
1108 n.state := sl_wblk2; -- next: start data msb
1109
1110 when sl_wblk2 => -- sl_wblk2: start wblk data msb -----
1111 n.din := RTBUF_DOB & r.dinl; -- setup din
1112 bcnt_dec := '1';
1113 ibcmd := c_bcmd_wblk; -- start rbus sequencer
1114 ibgo := '1';
1115 if bcnt_end = '0' then -- if not yet done
1116 irtreb := '1'; -- request next byte
1117 n.state := sl_wblkl; -- next: enter wblk pipe
1118 else -- all done
1119 n.state := sl_wwait0; -- next: wait for wdone
1120 end if;
1121
1122 when sl_wblkl => -- sl_wblkl: pipe wblk data lsb ------
1123 n.dinl := RTBUF_DOB; -- latch data lsb
1124 irtreb := '1'; -- request next byte
1125 bcnt_dec := '1';
1126 n.state := sl_wblkh; -- next: pipe msb
1127
1128 when sl_wblkh => -- sl_wblkh: pipe wblk data msb ------
1129 if B2L_WDONE = '1' then -- if last write done
1130 n.din := RTBUF_DOB & r.dinl; -- setup next din
1131 bcnt_dec := '1';
1132 if bcnt_end = '0' then -- if not yet done
1133 irtreb := '1';
1134 n.state := sl_wblkl; -- next: pipe lsb
1135 else -- all done
1136 n.state := sl_wwait0; -- next: wait last wdone
1137 end if;
1138 end if;
1139
1140 when sl_wwait0 => -- sl_wwait0: wait for wdone ---------
1141 if B2L_WDONE = '1' then
1142 if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
1143 n.state := sl_wwait1; -- next: wait for dcnt
1144 else
1145 n.state := sl_txstat; -- next: send stat
1146 end if;
1147 end if;
1148
1149 when sl_wwait1 => -- sl_wwait1: wait for dcnt ----------
1150 n.state := sl_txdcntl; -- next: send dcnt lsb
1151
1152 when sl_txdcntl => -- sl_txdcntl: send dcnt lsb ---------
1153 n.babo := R_BREGS.blkabo; -- remember blk abort
1154 ido := '0' & R_BREGS.dcnt(f_byte0); -- send dcnt lsb
1155 ival := '1';
1156 if RL_HOLD = '0' then -- wait for accept
1157 irtwea := '1';
1158 ocrcena := '1'; -- update output crc
1159 n.state := sl_txdcnth; -- next: send dcnt msb
1160 end if;
1161
1162 when sl_txdcnth => -- sl_txdcnth: send dcnt msb ---------
1163 ido := (others=>'0'); -- send dcnt msb
1164 ido(cntawidth-9 downto 0) := R_BREGS.dcnt(cntawidth-1 downto 8);
1165 ival := '1';
1166 if RL_HOLD = '0' then -- wait for accept
1167 irtwea := '1';
1168 ocrcena := '1'; -- update output crc
1169 n.state := sl_txstat; -- next: send stat
1170 end if;
1171
1172 when sl_txlabo => -- sl_txlabo: send labo flag ---------
1173 ido := '0' & "0000000" & r.babo; -- send babo
1174 ival := '1';
1175 if RL_HOLD = '0' then -- wait for accept
1176 irtwea := '1';
1177 ocrcena := '1'; -- update output crc
1178 n.state := sl_txstat; -- next: send stat
1179 end if;
1180
1181 when sl_attn => -- sl_attn: handle attention flags ---
1182 n.cnt := r.attn; -- use cnt to latch attn status
1183 n.attn := RB_LAM; -- LAM in current cycle send next time
1184 n.arpend := '0'; -- reenable attn nofification
1185 n.anreq := '0'; -- cancel pending notify requests
1186 n.state := sl_txcntl; -- next: send cnt lsb (holding attn)
1187
1188 when sl_txstat => -- sl_txstat: send status ------------
1189 ido(c_rlink_stat_rbf_stat) := R_BREGS.stat;
1190 ido(c_rlink_stat_rbf_attn) := has_attn;
1191 ido(c_rlink_stat_rbf_rbtout) := R_BREGS.rbtout;
1192 ido(c_rlink_stat_rbf_rbnak) := R_BREGS.rbnak;
1193 ido(c_rlink_stat_rbf_rberr) := R_BREGS.rberr;
1194 ival := '1';
1195 if RL_HOLD ='0' then -- wait for accept
1196 irtwea := '1';
1197 ocrcena := '1'; -- update output crc
1198 n.state := sl_txcrcl; -- next: send crc low
1199 end if;
1200
1201 when sl_txcrcl => -- sl_txcrcl: send crc low -----------
1202 ido := "0" & OCRC_OUT(f_byte0); -- send crc code low
1203 ival := '1';
1204 if RL_HOLD = '0' then -- wait for accept
1205 irtwea := not r.anact; -- no rtbuf for attn notify
1206 n.state := sl_txcrch; -- next: send crc high
1207 end if;
1208
1209 when sl_txcrch => -- sl_txcrch: send crc high ----------
1210 ido := "0" & OCRC_OUT(f_byte1); -- send crc code high
1211 -- here check for rtbuf overflow
1212 -- if space for 1 byte complete command and write crc
1213 if r.rtaddra_red = '0' then -- if space for 1 byte
1214 n.lcmd := r.rcmd; -- latch current command in lcmd
1215 ival := '1';
1216 if RL_HOLD = '0' then -- wait for accept
1217 irtwea := not r.anact; -- no rtbuf for attn notify
1218 -- if this was attn notify, back to idle
1219 if r.anact = '1' then
1220 n.state := sl_txeop; -- next: send eop
1221 -- here handle labo: if labo cmd and babo set, eat rest of list
1222 elsif r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_labo and
1223 r.babo='1' then
1224 n.state := sl_rxeop; -- next: wait for eop
1225 else
1226 n.state := sl_rxcmd; -- next: read command or eop
1227 end if;
1228 end if;
1229 else
1230 n.nakcode := c_rlink_nakcode_rtovfl; -- signal rtbuf ovfl
1231 n.state := sl_txnak; -- next: send nak
1232 end if;
1233
1234 when others => null; -- <> --------------------------------
1235
1236 end case;
1237
1238 -- addra logic (write pointer)
1239 if addra_clear = '1' then -- clear
1240 n.rtaddra := (others=>'0');
1241 n.rtaddra_red := '0';
1242 n.rtaddra_bad := '0';
1243 else
1244 if irtwea = '1' then -- inc when write on port a
1245 if r.rtaddra_red = '1' then -- if already red
1246 n. rtaddra_bad := '1'; -- than flag bad
1247 else -- still ok
1248 n.rtaddra := slv(unsigned(r.rtaddra) + 1); -- inc
1249 if r.rtaddra = rtaddr_tred then -- if inc'ed to red
1250 n. rtaddra_red := '1'; -- flag red
1251 end if;
1252 end if;
1253 end if;
1254 end if;
1255 if r.rtaddra = rtaddr_zero then
1256 n.rtaddra_zero := '1';
1257 else
1258 n.rtaddra_zero := '0';
1259 end if;
1260
1261 -- addrb logic (write and read pointer)
1262 if addrb_load = '1' then -- load
1263 if addrb_sela = '1' then
1264 n.rtaddrb := r.rtaddra;
1265 n.rtaddrb_red := r.rtaddra_red;
1266 n.rtaddrb_bad := r.rtaddra_bad;
1267 else
1268 n.rtaddrb := (others=>'0');
1269 n.rtaddrb_red := '0';
1270 n.rtaddrb_bad := '0';
1271 end if;
1272 else
1273 if irtreb = '1' or irtweb = '1' then -- inc when read/write on port b
1274 if r.rtaddrb_red = '1' then -- if already red
1275 n. rtaddrb_bad := '1'; -- than flag bad
1276 else -- still ok
1277 n.rtaddrb := slv(unsigned(r.rtaddrb) + 1); -- inc
1278 if r.rtaddrb = rtaddr_tred then -- if inc'ed to red
1279 n. rtaddrb_red := '1'; -- flag red
1280 end if;
1281 end if;
1282 end if;
1283 end if;
1284
1285 -- bcnt logic
1286 if bcnt_load = '1' then
1287 n.bcnt := bcnt_val;
1288 else
1289 if bcnt_dec ='1' then
1290 n.bcnt := slv(unsigned(r.bcnt) - 1);
1291 end if;
1292 end if;
1293
1294 N_LREGS <= n;
1295
1296 RL_BUSY_L <= ibusy;
1297 RL_DO_L <= ido;
1298 RL_VAL_L <= ival;
1299
1300 RL_MONI.eop <= r.moneop;
1301 RL_MONI.attn <= r.monattn;
1302 RL_MONI.lamp <= r.arpend;
1303
1304 DOFIFO_HOLD <= idohold;
1305
1306 RTBUF_WEA <= irtwea;
1307 RTBUF_DIA <= ido(d_f_data);
1308 RTBUF_ENB <= irtreb or irtweb;
1309 RTBUF_WEB <= irtweb;
1310 RTBUF_DIB <= idi8;
1311
1312 CRC_RESET <= crcreset;
1313 ICRC_ENA <= icrcena;
1314 OCRC_ENA <= ocrcena;
1315 OCRC_IN <= ido(d_f_data);
1316
1317 L2B_CMD <= ibcmd;
1318 L2B_GO <= ibgo;
1319
1320 end process proc_lnext;
1321
1322 -- bus FSM =================================================================
1323
1324 proc_bnext: process (R_BREGS, R_LREGS,
1325 RB_STAT, RB_SRES_TOT,
1326 DOFIFO_SIZE,
1327 L2B_CMD, L2B_GO)
1328
1329 variable r : bregs_type := bregs_init;
1330 variable n : bregs_type := bregs_init;
1331
1332 variable bto_go : slbit := '0';
1333 variable bto_end : slbit := '0';
1334 variable cnt_load : slbit := '0';
1335 variable cnt_dec : slbit := '0';
1336 variable cnt_end : slbit := '0';
1337 variable dcnt_clear : slbit := '0';
1338 variable dcnt_inc : slbit := '0';
1339 variable ival : slbit := '0';
1340 variable ido : slv8 := (others=>'0');
1341 variable iwdone : slbit := '0';
1342
1343 begin
1344
1345 r := R_BREGS;
1346 n := R_BREGS;
1347
1348 bto_go := '0'; -- default: keep rbus timeout in reset
1349 bto_end := '0';
1350 if unsigned(r.btocnt) = 0 then -- if rbus timeout count at zero
1351 bto_end := '1'; -- signal expiration
1352 end if;
1353
1354 cnt_load := '0';
1355 cnt_dec := '0';
1356 cnt_end := '0';
1357 if unsigned(r.cnt) = 0 then
1358 cnt_end := '1';
1359 end if;
1360
1361 dcnt_clear := '0';
1362 dcnt_inc := '0';
1363
1364 ival := '0';
1365 ido := (others=>'0');
1366
1367 iwdone := '0';
1368
1369 -- FIXME: what is proper almost full limit ?
1370 if unsigned(DOFIFO_SIZE) >= 28 then -- almost full
1371 n.wfifo := '1';
1372 elsif unsigned(DOFIFO_SIZE) <= 2 then -- almost empty
1373 n.wfifo := '0';
1374 end if;
1375
1376 n.rbinit := '0'; -- clear rb(init|aval|re|we) by default
1377 n.rbaval := '0'; -- they must always be set by the
1378 n.rbre := '0'; -- 'previous state'
1379 n.rbwe := '0'; --
1380
1381 case r.state is
1382
1383 when sb_idle => -- sb_idle: wait for cmd ------------
1384 if L2B_GO = '1' then -- if cmd seen
1385 n.stat := RB_STAT; -- always latch external status bits
1386 n.rbtout := '0';
1387 n.rbnak := '0';
1388 n.rberr := '0';
1389 n.blkabo := '0';
1390 n.dathpend := '0';
1391 dcnt_clear := '1';
1392 cnt_load := '1';
1393 case L2B_CMD is
1394 when c_bcmd_stat => -- stat ---------------------
1395 null; -- nothing else todo
1396 when c_bcmd_init => -- init ---------------------
1397 n.rbinit := '1'; -- send init pulse
1398 when c_bcmd_rblk => -- rblk ---------------------
1399 n.rbaval := '1'; -- start aval chunk
1400 n.state := sb_rstart; -- next: start rblk
1401 when c_bcmd_wblk => -- wblk ---------------------
1402 n.rbaval := '1'; -- start aval chunk
1403 n.state := sb_wstart; -- next: start wblk
1404 when others => null;
1405 end case;
1406 end if;
1407
1408 when sb_rstart => -- sb_rstart: start rblk -------------
1409 n.rbaval := '1'; -- extend aval
1410 n.rbre := '1'; -- start read cycle
1411 n.state := sb_rreg0; -- next: do rreg
1412
1413 when sb_rreg0 => -- sb_rreg0: rbus read cycle ---------
1414 ido := r.rbdout(f_byte1);
1415 n.stat := RB_STAT; -- follow external status bits
1416 if r.dathpend = '1' then -- if pending data msb
1417 ival := '1';
1418 n.dathpend := '0';
1419 end if;
1420 n.rbaval := '1'; -- extend aval
1421 bto_go := '1'; -- activate rbus timeout counter
1422 if RB_SRES_TOT.err = '1' then -- latch rbus error flag
1423 n.rberr := '1';
1424 n.blkabo := '1';
1425 end if;
1426 n.rbdout := RB_SRES_TOT.dout; -- latch data (follow till valid)
1427 if RB_SRES_TOT.busy='0' or bto_end='1' then -- wait non-busy or timeout
1428 if RB_SRES_TOT.busy='1' and bto_end='1' then -- if timeout and busy
1429 n.rbtout := '1'; -- set rbus timeout flag
1430 n.blkabo := '1';
1431 elsif RB_SRES_TOT.ack = '0' then -- if non-busy and no ack
1432 n.rbnak := '1'; -- set rbus nak flag
1433 n.blkabo := '1';
1434 end if;
1435 cnt_dec := '1';
1436 n.state := sb_rreg1; -- next: send data lsb
1437 else -- otherwise rbus read continues
1438 n.rbre := '1'; -- extend read cycle
1439 end if;
1440
1441 when sb_rreg1 => -- sb_rreg1: send read data ----------
1442 ido := r.rbdout(f_byte0);
1443 ival := '1'; -- send lsb
1444 n.dathpend := '1'; -- signal mdb pending
1445 dcnt_inc := not r.blkabo; -- inc dcnt if no error
1446 if cnt_end = '0' then -- if not yet done
1447 if r.blkabo = '0' then -- if no errors
1448 if r.wfifo = '0' then -- if fifo fine
1449 n.rbaval := '1'; -- extend aval
1450 n.rbre := '1'; -- start read cycle
1451 n.state := sb_rreg0; -- next: do rreg
1452 else -- fifo is full
1453 n.state := sb_rwait; -- next: fifo wait
1454 end if;
1455 else -- errors seen, rblk abort
1456 n.state := sb_rabo1; -- next: send rblk abort msb data
1457 end if;
1458 else -- all done
1459 n.state := sb_rend;
1460 end if;
1461
1462 when sb_rwait => -- sb_rwait: wait for fifo -----------
1463 if r.wfifo = '0' then -- if fifo fine
1464 n.rbaval := '1'; -- start aval chunk
1465 n.state := sb_rstart; -- restart rblk
1466 end if;
1467
1468 when sb_rend => -- sb_rend: send last read data ------
1469 ido := r.rbdout(f_byte1);
1470 ival := '1'; -- send msb
1471 n.dathpend := '0';
1472 n.state := sb_idle; -- next: idle
1473
1474 when sb_rabo0 => -- sb_rabo0: rblk abort, lsb data ----
1475 ido := (others=>'0');
1476 ival := '1';
1477 cnt_dec := '1';
1478 n.state := sb_rabo1; -- next: send rblk abort, msb data
1479
1480 when sb_rabo1 => -- sb_rabo1: rblk abort, msb data ----
1481 ido := (others=>'0');
1482 if r.wfifo = '0' then
1483 n.dathpend := '0'; -- cancel msb pend
1484 ival := '1';
1485 if cnt_end = '0' then -- if not yet done
1486 n.state := sb_rabo0; -- next: send rblk abort, lsb data
1487 else -- all done
1488 n.state := sb_idle; -- next: idle
1489 end if;
1490 end if;
1491
1492 when sb_wstart => -- sb_wstart: start wblk
1493 n.rbaval := '1'; -- start aval chunk
1494 n.rbwe := '1'; -- start write cycle
1495 n.state := sb_wreg0;
1496
1497 when sb_wreg0 => -- sb_wreg0: rbus write cycle
1498 n.stat := RB_STAT; -- follow external status bits
1499 n.rbaval := '1'; -- extend aval
1500 bto_go := '1'; -- activate rbus timeout counter
1501 if RB_SRES_TOT.err = '1' then -- latch rbus error flag
1502 n.rberr := '1';
1503 n.blkabo := '1';
1504 end if;
1505 if RB_SRES_TOT.busy='0' or bto_end='1' then -- wait non-busy or timeout
1506 if RB_SRES_TOT.busy='1' and bto_end='1' then -- if timeout and busy
1507 n.rbtout := '1'; -- set rbus timeout flag
1508 n.blkabo := '1';
1509 elsif RB_SRES_TOT.ack='0' then -- if non-busy and no ack
1510 n.rbnak := '1'; -- set rbus nak flag
1511 n.blkabo := '1';
1512 end if;
1513 cnt_dec := '1';
1514 iwdone := '1';
1515 n.state := sb_wreg1;
1516 else -- otherwise rbus write continues
1517 n.rbwe := '1'; -- extend write cycle
1518 end if;
1519
1520 when sb_wreg1 => -- sb_wreg1: wait write data
1521 dcnt_inc := not r.blkabo; -- inc dcnt if no error
1522 if cnt_end = '0' then -- if not yet done
1523 if r.blkabo = '0' then -- if no errors
1524 n.rbaval := '1'; -- extend aval
1525 n.rbwe := '1'; -- start write cycle
1526 n.state := sb_wreg0;
1527 else -- errors seen, rblk abort
1528 n.state := sb_wabo0; -- next: drop wblk rest
1529 end if;
1530 else -- all done
1531 n.state := sb_idle; -- next: idle
1532 end if;
1533
1534 when sb_wabo0 => -- sb_wabo0: wblk abort, drop data --
1535 iwdone := '1'; -- drop data
1536 cnt_dec := '1';
1537 n.state := sb_wabo1; -- next: wblk abort, wair
1538
1539 when sb_wabo1 => -- sb_wabo1: wblk abort, wait --------
1540 if cnt_end = '0' then -- if not yet done
1541 n.state := sb_wabo0; -- next: wblk abort, drop
1542 else -- all done
1543 n.state := sb_idle; -- next: idle
1544 end if;
1545
1546 when others => null; -- <> --------------------------------
1547
1548 end case;
1549
1550 if bto_go = '0' then -- handle access timeout counter
1551 n.btocnt := btocnt_init; -- if bto_go=0, keep in reset
1552 else
1553 n.btocnt := slv(unsigned(r.btocnt) - 1);-- otherwise count down
1554 end if;
1555
1556 if cnt_load = '1' then
1557 n.cnt := R_LREGS.cnt(cnt_f_dat);
1558 else
1559 if cnt_dec ='1' then
1560 n.cnt := slv(unsigned(r.cnt) - 1);
1561 end if;
1562 end if;
1563
1564 if dcnt_clear = '1' then
1565 n.dcnt := (others=>'0');
1566 else
1567 if dcnt_inc ='1' then
1568 n.dcnt := slv(unsigned(r.dcnt) + 1);
1569 end if;
1570 end if;
1571
1572 N_BREGS <= n;
1573
1574 DOFIFO_DI <= ido;
1575 DOFIFO_ENA <= ival;
1576
1577 B2L_WDONE <= iwdone;
1578
1579 end process proc_bnext;
1580
1581 -- config rbus iface =======================================================
1582
1583 proc_cnext: process (R_CREGS, R_LREGS, RBSEL, RB_MREQ_L)
1584
1585 variable r : cregs_type := cregs_init;
1586 variable n : cregs_type := cregs_init;
1587 variable irb_ack : slbit := '0';
1588 variable irb_dout : slv16 := (others=>'0');
1589
1590 begin
1591
1592 r := R_CREGS;
1593 n := R_CREGS;
1594
1595 irb_ack := '0';
1596 irb_dout := (others=>'0');
1597
1598 -- rbus transactions
1599 if RBSEL = '1' then
1600 irb_ack := RB_MREQ_L.re or RB_MREQ_L.we;
1601
1602 -- config register writes
1603 if RB_MREQ_L.we = '1' then
1604 case RB_MREQ_L.addr(1 downto 0) is
1605 when rbaddr_cntl =>
1606 n.anena := RB_MREQ_L.din(cntl_rbf_anena);
1607 n.atoena := RB_MREQ_L.din(cntl_rbf_atoena);
1608 n.atoval := RB_MREQ_L.din(cntl_rbf_atoval);
1609 when others => null;
1610 end case;
1611 end if;
1612
1613 -- rbus output driver
1614 case RB_MREQ_L.addr(1 downto 0) is
1615 when rbaddr_cntl =>
1616 irb_dout(cntl_rbf_anena) := r.anena;
1617 irb_dout(cntl_rbf_atoena) := r.atoena;
1618 irb_dout(cntl_rbf_atoval) := r.atoval;
1619 when rbaddr_stat =>
1620 irb_dout(stat_rbf_lcmd) := R_LREGS.lcmd;
1621 irb_dout(stat_rbf_babo) := R_LREGS.babo;
1622 irb_dout(stat_rbf_arpend) := R_LREGS.arpend;
1623 irb_dout(stat_rbf_rbsize) := slv(to_unsigned(RTAWIDTH-10,3));
1624 when rbaddr_id0 =>
1625 irb_dout := SYSID(15 downto 0);
1626 when rbaddr_id1 =>
1627 irb_dout := SYSID(31 downto 16);
1628 when others => null;
1629 end case;
1630
1631 end if;
1632
1633 N_CREGS <= n;
1634
1635 RB_SRES_CONF.dout <= irb_dout;
1636 RB_SRES_CONF.ack <= irb_ack;
1637 RB_SRES_CONF.err <= '0';
1638 RB_SRES_CONF.busy <= '0';
1639
1640 end process proc_cnext;
1641
1642 -- rbus driver -----------------------------------------------------
1643
1644 proc_mreq: process (R_LREGS, R_BREGS)
1645 begin
1646
1647 RB_MREQ_L <= rb_mreq_init;
1648 RB_MREQ_L.aval <= R_BREGS.rbaval;
1649 RB_MREQ_L.re <= R_BREGS.rbre;
1650 RB_MREQ_L.we <= R_BREGS.rbwe;
1651 RB_MREQ_L.init <= R_BREGS.rbinit;
1652 RB_MREQ_L.addr <= R_LREGS.addr;
1653 RB_MREQ_L.din <= R_LREGS.din;
1654
1655 end process proc_mreq;
1656
1657 RB_MREQ <= RB_MREQ_L;
1658
1659 RL_BUSY <= RL_BUSY_L;
1660 RL_DO <= RL_DO_L;
1661 RL_VAL <= RL_VAL_L;
1662
1663-- synthesis translate_off
1664
1665 RLMON: if ENAPIN_RLMON >= 0 generate
1666 MON : rlink_mon_sb
1667 generic map (
1668 DWIDTH => RL_DI'length,
1669 ENAPIN => ENAPIN_RLMON)
1670 port map (
1671 CLK => CLK,
1672 RL_DI => RL_DI,
1673 RL_ENA => RL_ENA,
1674 RL_BUSY => RL_BUSY_L,
1675 RL_DO => RL_DO_L,
1676 RL_VAL => RL_VAL_L,
1677 RL_HOLD => RL_HOLD
1678 );
1679 end generate RLMON;
1680
1681 RBMON: if ENAPIN_RBMON >= 0 generate
1682 MON : rb_mon_sb
1683 generic map (
1684 DBASE => 8,
1685 ENAPIN => ENAPIN_RBMON)
1686 port map (
1687 CLK => CLK,
1688 RB_MREQ => RB_MREQ_L,
1689 RB_SRES => RB_SRES_TOT,
1690 RB_LAM => RB_LAM,
1691 RB_STAT => RB_STAT
1692 );
1693 end generate RBMON;
1694
1695-- synthesis translate_on
1696
1697end syn;
crc16
Definition: crc16.vhd:31
fifo_1c_dram
Definition: fifo_1c_dram.vhd:34
fifo_1c_dram.RESET
in RESET slbit
Definition: fifo_1c_dram.vhd:40
fifo_1c_dram.ENA
in ENA slbit
Definition: fifo_1c_dram.vhd:42
fifo_1c_dram.DO
out DO slv( DWIDTH- 1 downto 0)
Definition: fifo_1c_dram.vhd:44
fifo_1c_dram.DI
in DI slv( DWIDTH- 1 downto 0)
Definition: fifo_1c_dram.vhd:41
fifo_1c_dram.BUSY
out BUSY slbit
Definition: fifo_1c_dram.vhd:43
fifo_1c_dram.HOLD
in HOLD slbit
Definition: fifo_1c_dram.vhd:46
fifo_1c_dram.CLK
in CLK slbit
Definition: fifo_1c_dram.vhd:39
fifo_1c_dram.VAL
out VAL slbit
Definition: fifo_1c_dram.vhd:45
fifo_1c_dram.AWIDTH
AWIDTH positive := 7
Definition: fifo_1c_dram.vhd:36
fifo_1c_dram.SIZE
out SIZE slv( AWIDTH downto 0)
Definition: fifo_1c_dram.vhd:48
fifo_1c_dram.DWIDTH
DWIDTH positive := 16
Definition: fifo_1c_dram.vhd:37
ram_2swsr_rfirst_gen
Definition: ram_2swsr_rfirst_gen.vhd:33
ram_2swsr_rfirst_gen.WEA
in WEA slbit
Definition: ram_2swsr_rfirst_gen.vhd:42
ram_2swsr_rfirst_gen.ENA
in ENA slbit
Definition: ram_2swsr_rfirst_gen.vhd:40
ram_2swsr_rfirst_gen.DIA
in DIA slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_rfirst_gen.vhd:46
ram_2swsr_rfirst_gen.ENB
in ENB slbit
Definition: ram_2swsr_rfirst_gen.vhd:41
ram_2swsr_rfirst_gen.ADDRB
in ADDRB slv( AWIDTH- 1 downto 0)
Definition: ram_2swsr_rfirst_gen.vhd:45
ram_2swsr_rfirst_gen.CLKA
in CLKA slbit
Definition: ram_2swsr_rfirst_gen.vhd:38
ram_2swsr_rfirst_gen.ADDRA
in ADDRA slv( AWIDTH- 1 downto 0)
Definition: ram_2swsr_rfirst_gen.vhd:44
ram_2swsr_rfirst_gen.AWIDTH
AWIDTH positive := 11
Definition: ram_2swsr_rfirst_gen.vhd:35
ram_2swsr_rfirst_gen.CLKB
in CLKB slbit
Definition: ram_2swsr_rfirst_gen.vhd:39
ram_2swsr_rfirst_gen.DOB
out DOB slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_rfirst_gen.vhd:50
ram_2swsr_rfirst_gen.DIB
in DIB slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_rfirst_gen.vhd:47
ram_2swsr_rfirst_gen.DOA
out DOA slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_rfirst_gen.vhd:48
ram_2swsr_rfirst_gen.WEB
in WEB slbit
Definition: ram_2swsr_rfirst_gen.vhd:43
ram_2swsr_rfirst_gen.DWIDTH
DWIDTH positive := 9
Definition: ram_2swsr_rfirst_gen.vhd:36
rb_mon_sb
Definition: rb_mon_sb.vhd:38
rb_mon_sb.DBASE
DBASE positive := 2
Definition: rb_mon_sb.vhd:40
rb_mon_sb.CLK
in CLK slbit
Definition: rb_mon_sb.vhd:43
rb_mon_sb.RB_MREQ
in RB_MREQ rb_mreq_type
Definition: rb_mon_sb.vhd:44
rb_mon_sb.ENAPIN
ENAPIN integer := sbcntl_sbf_rbmon
Definition: rb_mon_sb.vhd:41
rb_mon_sb.RB_STAT
in RB_STAT slv4
Definition: rb_mon_sb.vhd:48
rb_mon_sb.RB_LAM
in RB_LAM slv16 :=( others => '0')
Definition: rb_mon_sb.vhd:46
rb_mon_sb.RB_SRES
in RB_SRES rb_sres_type
Definition: rb_mon_sb.vhd:45
rb_sel
Definition: rb_sel.vhd:29
rb_sres_or_2
Definition: rb_sres_or_2.vhd:30
rb_sres_or_2.RB_SRES_2
in RB_SRES_2 rb_sres_type := rb_sres_init
Definition: rb_sres_or_2.vhd:33
rb_sres_or_2.RB_SRES_OR
out RB_SRES_OR rb_sres_type
Definition: rb_sres_or_2.vhd:35
rb_sres_or_2.RB_SRES_1
in RB_SRES_1 rb_sres_type
Definition: rb_sres_or_2.vhd:32
rblib
Definition: rblib.vhd:32
rlink_core.syn
Definition: rlink_core.vhd:185
rlink_core.syn.bregs_type
bregs_type
Definition: rlink_core.vhd:341
rlink_core.syn.N_BREGS
bregs_type N_BREGS
Definition: rlink_core.vhd:391
rlink_core.syn.OCRC_OUT
slv16 :=( others => '0') OCRC_OUT
Definition: rlink_core.vhd:413
rlink_core.syn.c_eop
slv3 := "001" c_eop
Definition: rlink_core.vhd:211
rlink_core.syn.DOFIFO_SIZE
slv6 :=( others => '0') DOFIFO_SIZE
Definition: rlink_core.vhd:407
rlink_core.syn.RTBUF_DIB
slv8 :=( others => '0') RTBUF_DIB
Definition: rlink_core.vhd:399
rlink_core.syn.DOFIFO_ENA
slbit := '0' DOFIFO_ENA
Definition: rlink_core.vhd:403
rlink_core.syn.DOFIFO_DO
slv8 :=( others => '0') DOFIFO_DO
Definition: rlink_core.vhd:404
rlink_core.syn.RL_DO_L
slv9 :=( others => '0') RL_DO_L
Definition: rlink_core.vhd:424
rlink_core.syn.RBSEL
slbit := '0' RBSEL
Definition: rlink_core.vhd:416
rlink_core.syn.rtaddr_tred
slv( RTAWIDTH- 1 downto 0) :=( 0=> '0', others => '1') rtaddr_tred
Definition: rlink_core.vhd:299
rlink_core.syn.f_byte1
integer range 15 downto 8 f_byte1
Definition: rlink_core.vhd:197
rlink_core.syn.stat_rbf_lcmd
integer range 15 downto 8 stat_rbf_lcmd
Definition: rlink_core.vhd:203
rlink_core.syn.d_f_data
integer range 7 downto 0 d_f_data
Definition: rlink_core.vhd:195
rlink_core.syn.RTBUF_DOB
slv8 :=( others => '0') RTBUF_DOB
Definition: rlink_core.vhd:400
rlink_core.syn.DOFIFO_HOLD
slbit := '0' DOFIFO_HOLD
Definition: rlink_core.vhd:406
rlink_core.syn.rbaddr_id1
slv2 := "01" rbaddr_id1
Definition: rlink_core.vhd:190
rlink_core.syn.cnt_zero
slv( cntawidth- 1 downto 0) :=( others => '0') cnt_zero
Definition: rlink_core.vhd:361
rlink_core.syn.c_sop
slv3 := "000" c_sop
Definition: rlink_core.vhd:210
rlink_core.syn.c_bcmd_rblk
slv2 := "10" c_bcmd_rblk
Definition: rlink_core.vhd:217
rlink_core.syn.rbaddr
slv16 := x"fffc" rbaddr
Definition: rlink_core.vhd:187
rlink_core.syn.cntawidth
positive := RTAWIDTH- 1 cntawidth
Definition: rlink_core.vhd:220
rlink_core.syn.f_byte0
integer range 7 downto 0 f_byte0
Definition: rlink_core.vhd:198
rlink_core.syn.N_CREGS
cregs_type := cregs_init N_CREGS
Definition: rlink_core.vhd:393
rlink_core.syn.RB_MREQ_L
rb_mreq_type := rb_mreq_init RB_MREQ_L
Definition: rlink_core.vhd:418
rlink_core.syn.stat_rbf_babo
integer := 7 stat_rbf_babo
Definition: rlink_core.vhd:204
rlink_core.syn.rbaddr_cntl
slv2 := "11" rbaddr_cntl
Definition: rlink_core.vhd:188
rlink_core.syn.OCRC_ENA
slbit := '0' OCRC_ENA
Definition: rlink_core.vhd:411
rlink_core.syn.rtaddr_zero
slv( RTAWIDTH- 1 downto 0) :=( others => '0') rtaddr_zero
Definition: rlink_core.vhd:298
rlink_core.syn.RTBUF_DIA
slv8 :=( others => '0') RTBUF_DIA
Definition: rlink_core.vhd:398
rlink_core.syn.ICRC_ENA
slbit := '0' ICRC_ENA
Definition: rlink_core.vhd:410
rlink_core.syn.cntl_rbf_atoval
integer range 7 downto 0 cntl_rbf_atoval
Definition: rlink_core.vhd:202
rlink_core.syn.R_BREGS
bregs_type := bregs_init R_BREGS
Definition: rlink_core.vhd:390
rlink_core.syn.RB_SRES_CLEAN
rb_sres_type := rb_sres_init RB_SRES_CLEAN
Definition: rlink_core.vhd:419
rlink_core.syn.L2B_CMD
slv2 :=( others => '0') L2B_CMD
Definition: rlink_core.vhd:428
rlink_core.syn.lregs_type
lregs_type
Definition: rlink_core.vhd:267
rlink_core.syn.stat_rbf_rbsize
integer range 2 downto 0 stat_rbf_rbsize
Definition: rlink_core.vhd:206
rlink_core.syn.c_attn
slv3 := "011" c_attn
Definition: rlink_core.vhd:213
rlink_core.syn.RB_SRES_TOT
rb_sres_type := rb_sres_init RB_SRES_TOT
Definition: rlink_core.vhd:421
rlink_core.syn.B2L_WDONE
slbit := '0' B2L_WDONE
Definition: rlink_core.vhd:429
rlink_core.syn.btocnt_init
slv( BTOWIDTH- 1 downto 0) :=( others => '1') btocnt_init
Definition: rlink_core.vhd:360
rlink_core.syn.rbaddr_id0
slv2 := "00" rbaddr_id0
Definition: rlink_core.vhd:191
rlink_core.syn.R_CREGS
cregs_type := cregs_init R_CREGS
Definition: rlink_core.vhd:392
rlink_core.syn.RTBUF_WEA
slbit := '0' RTBUF_WEA
Definition: rlink_core.vhd:396
rlink_core.syn.c_nak
slv3 := "010" c_nak
Definition: rlink_core.vhd:212
rlink_core.syn.d_f_ctyp
integer range 2 downto 0 d_f_ctyp
Definition: rlink_core.vhd:194
rlink_core.syn.L2B_GO
slbit := '0' L2B_GO
Definition: rlink_core.vhd:427
rlink_core.syn.bregs_init
bregs_type :=( sb_idle, '0', '0', '0', '0',( others => '0'), '0', '0', '0', '0', cnt_zero, cnt_zero, btocnt_init, '0', '0',( others => '0')) bregs_init
Definition: rlink_core.vhd:363
rlink_core.syn.RB_SRES_CONF
rb_sres_type := rb_sres_init RB_SRES_CONF
Definition: rlink_core.vhd:420
rlink_core.syn.cregs_type
cregs_type
Definition: rlink_core.vhd:377
rlink_core.syn.rbaddr_stat
slv2 := "10" rbaddr_stat
Definition: rlink_core.vhd:189
rlink_core.syn.N_LREGS
lregs_type N_LREGS
Definition: rlink_core.vhd:389
rlink_core.syn.c_bcmd_wblk
slv2 := "11" c_bcmd_wblk
Definition: rlink_core.vhd:218
rlink_core.syn.RTBUF_ENB
slbit := '0' RTBUF_ENB
Definition: rlink_core.vhd:395
rlink_core.syn.lregs_init
lregs_type :=( sl_idle,( others => '0'),( others => '1'),( others => '0'),( others => '0'),( others => '0'), bcnt_zero,( others => '0'), '0', '0', '0',( others => '0'), '0', '0',( others => '0'), '0', '0',( others => '0'), rtaddr_zero, '0', '0', '0', rtaddr_zero, '0', '0', '0', '0') lregs_init
Definition: rlink_core.vhd:301
rlink_core.syn.DOFIFO_VAL
slbit := '0' DOFIFO_VAL
Definition: rlink_core.vhd:405
rlink_core.syn.RL_VAL_L
slbit := '0' RL_VAL_L
Definition: rlink_core.vhd:425
rlink_core.syn.DOFIFO_DI
slv8 :=( others => '0') DOFIFO_DI
Definition: rlink_core.vhd:402
rlink_core.syn.cregs_init
cregs_type :=( '0', '0',( others => '0')) cregs_init
Definition: rlink_core.vhd:383
rlink_core.syn.cntl_rbf_atoena
integer := 14 cntl_rbf_atoena
Definition: rlink_core.vhd:201
rlink_core.syn.bstate_type
(sb_idle,sb_rstart,sb_rreg0,sb_rreg1,sb_rwait,sb_rend,sb_rabo0,sb_rabo1,sb_wstart,sb_wreg0,sb_wreg1,sb_wabo0,sb_wabo1) bstate_type
Definition: rlink_core.vhd:325
rlink_core.syn.cnt_f_dat
integer range cntawidth- 1 downto 0 cnt_f_dat
Definition: rlink_core.vhd:221
rlink_core.syn.stat_rbf_arpend
integer := 6 stat_rbf_arpend
Definition: rlink_core.vhd:205
rlink_core.syn.R_LREGS
lregs_type := lregs_init R_LREGS
Definition: rlink_core.vhd:388
rlink_core.syn.c_bcmd_init
slv2 := "01" c_bcmd_init
Definition: rlink_core.vhd:216
rlink_core.syn.ICRC_OUT
slv16 :=( others => '0') ICRC_OUT
Definition: rlink_core.vhd:412
rlink_core.syn.d_f_cflag
integer := 8 d_f_cflag
Definition: rlink_core.vhd:193
rlink_core.syn.OCRC_IN
slv8 :=( others => '0') OCRC_IN
Definition: rlink_core.vhd:414
rlink_core.syn.cntl_rbf_anena
integer := 15 cntl_rbf_anena
Definition: rlink_core.vhd:200
rlink_core.syn.CRC_RESET
slbit := '0' CRC_RESET
Definition: rlink_core.vhd:409
rlink_core.syn.RL_BUSY_L
slbit := '0' RL_BUSY_L
Definition: rlink_core.vhd:423
rlink_core.syn.RTBUF_WEB
slbit := '0' RTBUF_WEB
Definition: rlink_core.vhd:397
rlink_core.syn.c_bcmd_stat
slv2 := "00" c_bcmd_stat
Definition: rlink_core.vhd:215
rlink_core.syn.bcnt_zero
slv( RTAWIDTH- 1 downto 0) :=( others => '0') bcnt_zero
Definition: rlink_core.vhd:297
rlink_core.syn.lstate_type
(sl_idle,sl_txanot,sl_txsop,sl_txnak,sl_txnakcode,sl_txrtbuf,sl_txeop,sl_rxeop,sl_rxcmd,sl_rxaddrl,sl_rxaddrh,sl_rxdatl,sl_rxdath,sl_rxcntl,sl_rxcnth,sl_rxccrcl,sl_rxccrch,sl_txcmd,sl_txcntl,sl_txcnth,sl_rstart,sl_txdat,sl_wblk,sl_rxwblk,sl_rxdcrcl,sl_rxdcrch,sl_wblk0,sl_wblk1,sl_wblk2,sl_wblkl,sl_wblkh,sl_wwait0,sl_wwait1,sl_txdcntl,sl_txdcnth,sl_txlabo,sl_attn,sl_txstat,sl_txcrcl,sl_txcrch) lstate_type
Definition: rlink_core.vhd:224
rlink_core
Definition: rlink_core.vhd:156
rlink_core.RESET
in RESET slbit
Definition: rlink_core.vhd:166
rlink_core.ENAPIN_RBMON
ENAPIN_RBMON integer :=- 1
Definition: rlink_core.vhd:162
rlink_core.BTOWIDTH
BTOWIDTH positive := 5
Definition: rlink_core.vhd:158
rlink_core.RL_HOLD
in RL_HOLD slbit
Definition: rlink_core.vhd:172
rlink_core.RTAWIDTH
RTAWIDTH positive := 12
Definition: rlink_core.vhd:159
rlink_core.RB_LAM
in RB_LAM slv16
Definition: rlink_core.vhd:176
rlink_core.ENAPIN_RLMON
ENAPIN_RLMON integer :=- 1
Definition: rlink_core.vhd:161
rlink_core.RL_DI
in RL_DI slv9
Definition: rlink_core.vhd:167
rlink_core.RL_VAL
out RL_VAL slbit
Definition: rlink_core.vhd:171
rlink_core.fsm_encoding
string fsm_encoding
Definition: rlink_core.vhd:180
rlink_core.CLK
in CLK slbit
Definition: rlink_core.vhd:164
rlink_core.RB_MREQ
out RB_MREQ rb_mreq_type
Definition: rlink_core.vhd:174
rlink_core.RL_BUSY
out RL_BUSY slbit
Definition: rlink_core.vhd:169
rlink_core.RB_STAT
in RB_STAT slv4
Definition: rlink_core.vhd:178
rlink_core.CE_INT
in CE_INT slbit := '0'
Definition: rlink_core.vhd:165
rlink_core.RB_SRES
in RB_SRES rb_sres_type
Definition: rlink_core.vhd:175
rlink_core.RL_DO
out RL_DO slv9
Definition: rlink_core.vhd:170
rlink_core.RL_ENA
in RL_ENA slbit
Definition: rlink_core.vhd:168
rlink_core.RL_MONI
out RL_MONI rl_moni_type
Definition: rlink_core.vhd:173
rlink_core.SYSID
SYSID slv32 :=( others => '0')
Definition: rlink_core.vhd:160
rlink_mon_sb
Definition: rlink_mon_sb.vhd:32
rlink_mon_sb.RL_DI
in RL_DI slv( DWIDTH- 1 downto 0)
Definition: rlink_mon_sb.vhd:38
rlink_mon_sb.RL_HOLD
in RL_HOLD slbit
Definition: rlink_mon_sb.vhd:44
rlink_mon_sb.RL_VAL
in RL_VAL slbit
Definition: rlink_mon_sb.vhd:42
rlink_mon_sb.RL_DO
in RL_DO slv( DWIDTH- 1 downto 0)
Definition: rlink_mon_sb.vhd:41
rlink_mon_sb.ENAPIN
ENAPIN integer := sbcntl_sbf_rlmon
Definition: rlink_mon_sb.vhd:35
rlink_mon_sb.CLK
in CLK slbit
Definition: rlink_mon_sb.vhd:37
rlink_mon_sb.RL_BUSY
in RL_BUSY slbit
Definition: rlink_mon_sb.vhd:40
rlink_mon_sb.DWIDTH
DWIDTH positive := 9
Definition: rlink_mon_sb.vhd:34
rlink_mon_sb.RL_ENA
in RL_ENA slbit
Definition: rlink_mon_sb.vhd:39
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
slvtypes.slv3
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
slvtypes.slv9
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
slvtypes.slv32
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30
slvtypes.slv6
std_logic_vector( 5 downto 0) slv6
Definition: slvtypes.vhd:38
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
slvtypes.slv2
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slvtypes.slv
std_logic_vector slv
Definition: slvtypes.vhd:31