w11 - vhd 0.794
W11 CPU core and support modules
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ram_2swsr_rfirst_gen Entity Reference
Inheritance diagram for ram_2swsr_rfirst_gen:
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Collaboration diagram for ram_2swsr_rfirst_gen:
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Entities

syn  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
numeric_std 
slvtypes  Package <slvtypes>
vcomponents 
memlib  Package <memlib>

Generics

AWIDTH  positive := 11
DWIDTH  positive := 9

Ports

CLKA   in   slbit
CLKB   in   slbit
ENA   in   slbit
ENB   in   slbit
WEA   in   slbit
WEB   in   slbit
ADDRA   in   slv ( AWIDTH - 1 downto 0 )
ADDRB   in   slv ( AWIDTH - 1 downto 0 )
DIA   in   slv ( DWIDTH - 1 downto 0 )
DIB   in   slv ( DWIDTH - 1 downto 0 )
DOA   out   slv ( DWIDTH - 1 downto 0 )
DOB   out   slv ( DWIDTH - 1 downto 0 )

Detailed Description

Definition at line 33 of file ram_2swsr_rfirst_gen.vhd.

Member Data Documentation

◆ AWIDTH

AWIDTH positive := 11
Generic

Definition at line 35 of file ram_2swsr_rfirst_gen.vhd.

◆ DWIDTH

DWIDTH positive := 9
Generic

Definition at line 36 of file ram_2swsr_rfirst_gen.vhd.

◆ CLKA

CLKA in slbit
Port

Definition at line 38 of file ram_2swsr_rfirst_gen.vhd.

◆ CLKB

CLKB in slbit
Port

Definition at line 39 of file ram_2swsr_rfirst_gen.vhd.

◆ ENA

ENA in slbit
Port

Definition at line 40 of file ram_2swsr_rfirst_gen.vhd.

◆ ENB

ENB in slbit
Port

Definition at line 41 of file ram_2swsr_rfirst_gen.vhd.

◆ WEA

WEA in slbit
Port

Definition at line 42 of file ram_2swsr_rfirst_gen.vhd.

◆ WEB

WEB in slbit
Port

Definition at line 43 of file ram_2swsr_rfirst_gen.vhd.

◆ ADDRA

ADDRA in slv ( AWIDTH - 1 downto 0 )
Port

Definition at line 44 of file ram_2swsr_rfirst_gen.vhd.

◆ ADDRB

ADDRB in slv ( AWIDTH - 1 downto 0 )
Port

Definition at line 45 of file ram_2swsr_rfirst_gen.vhd.

◆ DIA

DIA in slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 46 of file ram_2swsr_rfirst_gen.vhd.

◆ DIB

DIB in slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 47 of file ram_2swsr_rfirst_gen.vhd.

◆ DOA

DOA out slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 48 of file ram_2swsr_rfirst_gen.vhd.

◆ DOB

DOB out slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 50 of file ram_2swsr_rfirst_gen.vhd.

◆ ieee

ieee
Library

Definition at line 27 of file ram_2swsr_rfirst_gen.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 28 of file ram_2swsr_rfirst_gen.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 29 of file ram_2swsr_rfirst_gen.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 31 of file ram_2swsr_rfirst_gen.vhd.

◆ unisim

unisim
Library

Definition at line 24 of file ram_2swsr_rfirst_gen_unisim.vhd.

◆ vcomponents

vcomponents
use clause

Definition at line 25 of file ram_2swsr_rfirst_gen_unisim.vhd.

◆ memlib

memlib
use clause

Definition at line 28 of file ram_2swsr_rfirst_gen_unisim.vhd.


The documentation for this design unit was generated from the following files: