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W11 CPU core and support modules
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tb_tst_serloop2_n4.vhd
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1-- $Id: tb_tst_serloop2_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_tst_serloop2_n4 - sim
7-- Description: Test bench for sys_tst_serloop2_n4
8--
9-- Dependencies: simlib/simclk
10-- xlib/sfs_gsim_core
11-- sys_tst_serloop2_n4 [UUT]
12-- tb/tb_tst_serloop
13--
14-- To test: sys_tst_serloop2_n4
15--
16-- Target Devices: generic
17--
18-- Revision History:
19-- Date Rev Version Comment
20-- 2018-11-03 1064 1.1.1 use sfs_gsim_core
21-- 2016-09-03 805 1.1 remove CLK_STOP logic (simstop via report)
22-- 2016-04-09 760 1.0 Initial version (cloned from tb_tst_serloop1_n4)
23------------------------------------------------------------------------------
24
25library ieee;
26use ieee.std_logic_1164.all;
27use ieee.numeric_std.all;
28use ieee.std_logic_textio.all;
29use std.textio.all;
30
31use work.slvtypes.all;
32use work.xlib.all;
33use work.simlib.all;
34use work.sys_conf.all;
35
38
39architecture sim of tb_tst_serloop2_n4 is
40
41 signal CLK100 : slbit := '0';
42
43 signal CLKS : slbit := '0';
44 signal CLKH : slbit := '0';
45
46 signal I_RXD : slbit := '1';
47 signal O_TXD : slbit := '1';
48 signal O_RTS_N : slbit := '0';
49 signal I_CTS_N : slbit := '0';
50 signal I_SWI : slv16 := (others=>'0');
51 signal I_BTN : slv5 := (others=>'0');
52
53 signal RXD : slbit := '1';
54 signal TXD : slbit := '1';
55 signal RTS_N : slbit := '0';
56 signal CTS_N : slbit := '0';
57 signal SWI : slv16 := (others=>'0');
58 signal BTN : slv5 := (others=>'0');
59
60 constant clock_period : Delay_length := 10 ns;
61 constant clock_offset : Delay_length := 200 ns;
62 constant delay_time : Delay_length := 2 ns;
63
64begin
65
66 SYSCLK : simclk
67 generic map (
70 port map (
71 CLK => CLK100
72 );
73
74 GEN_CLKSYS : sfs_gsim_core
75 generic map (
76 VCO_DIVIDE => sys_conf_clksys_vcodivide,
77 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
78 OUT_DIVIDE => sys_conf_clksys_outdivide)
79 port map (
80 CLKIN => CLK100,
81 CLKFX => CLKH,
82 LOCKED => open
83 );
84
85 GEN_CLKSER : sfs_gsim_core
86 generic map (
87 VCO_DIVIDE => sys_conf_clkser_vcodivide,
88 VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
89 OUT_DIVIDE => sys_conf_clkser_outdivide)
90 port map (
91 CLKIN => CLK100,
92 CLKFX => CLKS,
93 LOCKED => open
94 );
95
96 UUT : entity work.sys_tst_serloop2_n4
97 port map (
99 I_RXD => I_RXD,
100 O_TXD => O_TXD,
101 O_RTS_N => O_RTS_N,
102 I_CTS_N => I_CTS_N,
103 I_SWI => I_SWI,
104 I_BTN => I_BTN,
105 I_BTNRST_N => '1',
106 O_LED => open,
107 O_RGBLED0 => open,
108 O_RGBLED1 => open,
109 O_ANO_N => open,
110 O_SEG_N => open
111 );
112
113 GENTB : entity work.tb_tst_serloop
114 port map (
115 CLKS => CLKS,
116 CLKH => CLKH,
117 P0_RXD => RXD,
118 P0_TXD => TXD,
119 P0_RTS_N => RTS_N,
120 P0_CTS_N => CTS_N,
121 P1_RXD => open, -- port 1 unused for n4 !
122 P1_TXD => '0',
123 P1_RTS_N => '0',
124 P1_CTS_N => open,
125 SWI => SWI(7 downto 0),
126 BTN => BTN(3 downto 0)
127 );
128
129 I_RXD <= RXD after delay_time;
130 TXD <= O_TXD after delay_time;
131 RTS_N <= O_RTS_N after delay_time;
132 I_CTS_N <= CTS_N after delay_time;
133
134 I_SWI <= SWI after delay_time;
135 I_BTN <= BTN after delay_time;
136
137end sim;
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
Delay_length := 2 ns delay_time
Delay_length := 10 ns clock_period
slv16 :=( others => '0') SWI
Delay_length := 200 ns clock_offset
slv5 :=( others => '0') I_BTN
slv5 :=( others => '0') BTN
slv16 :=( others => '0') I_SWI
out P0_RXD slbit
in P1_RTS_N slbit
in P1_TXD slbit
in P0_TXD slbit
out P0_CTS_N slbit
out P1_RXD slbit
in P0_RTS_N slbit
out P1_CTS_N slbit
Definition: xlib.vhd:35