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W11 CPU core and support modules
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sys_tst_serloop2_n4.vhd
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1-- $Id: sys_tst_serloop2_n4.vhd 1369 2023-02-08 18:59:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_serloop2_n4 - syn
7-- Description: Serial link tester design for nexys4 (serport_2clock case)
8--
9-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
10-- bpgen/bp_rs232_4line_iob
11-- bpgen/sn_humanio
12-- tst_serloop_hiomap
13-- vlib/serport/serport_2clock2
14-- tst_serloop
15--
16-- Test bench: -
17--
18-- Target Devices: generic
19-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
20--
21-- Synthesized:
22-- Date Rev viv Target flop lutl lutm bram slic
23-- 2019-02-02 1108 2018.3 xc7a100t-1 537 512 16 0 236
24-- 2019-02-02 1108 2017.2 xc7a100t-1 537 549 16 0 238
25--
26-- Revision History:
27-- Date Rev Version Comment
28-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce
29-- 2016-06-05 722 1.0.1 use CDUWIDTH=7 for CLKS, 120 MHz is natural choice
30-- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n4)
31------------------------------------------------------------------------------
32--
33
34library ieee;
35use ieee.std_logic_1164.all;
36use ieee.numeric_std.all;
37
38use work.slvtypes.all;
39use work.bpgenlib.all;
40use work.tst_serlooplib.all;
41use work.serportlib.all;
42use work.sys_conf.all;
43
44-- ----------------------------------------------------------------------------
45
46entity sys_tst_serloop2_n4 is -- top level
47 -- implements nexys4_aif
48 port (
49 I_CLK100 : in slbit; -- 100 MHz clock
50 I_RXD : in slbit; -- receive data (board view)
51 O_TXD : out slbit; -- transmit data (board view)
52 O_RTS_N : out slbit; -- rx rts (board view; act.low)
53 I_CTS_N : in slbit; -- tx cts (board view; act.low)
54 I_SWI : in slv16; -- n4 switches
55 I_BTN : in slv5; -- n4 buttons
56 I_BTNRST_N : in slbit; -- n4 reset button
57 O_LED : out slv16; -- n4 leds
58 O_RGBLED0 : out slv3; -- n4 rgb-led 0
59 O_RGBLED1 : out slv3; -- n4 rgb-led 1
60 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
61 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
62 );
64
65architecture syn of sys_tst_serloop2_n4 is
66
67 signal CLK : slbit := '0';
68 signal RESET : slbit := '0';
69
70 signal CE_USEC : slbit := '0';
71 signal CE_MSEC : slbit := '0';
72
73 signal CLKS : slbit := '0';
74 signal CES_MSEC : slbit := '0';
75
76 signal RXD : slbit := '0';
77 signal TXD : slbit := '0';
78 signal CTS_N : slbit := '0';
79 signal RTS_N : slbit := '0';
80
81 signal SWI : slv16 := (others=>'0');
82 signal BTN : slv5 := (others=>'0');
83 signal LED : slv16 := (others=>'0');
84 signal DSP_DAT : slv32 := (others=>'0');
85 signal DSP_DP : slv8 := (others=>'0');
86
87 signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
88 signal HIO_STAT : hio_stat_type := hio_stat_init;
89
90 signal RXDATA : slv8 := (others=>'0');
91 signal RXVAL : slbit := '0';
92 signal RXHOLD : slbit := '0';
93 signal TXDATA : slv8 := (others=>'0');
94 signal TXENA : slbit := '0';
95 signal TXBUSY : slbit := '0';
96
97 signal SER_MONI : serport_moni_type := serport_moni_init;
98
99begin
100
101 GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
102 generic map (
103 CLKIN_PERIOD => 10.0,
104 CLKIN_JITTER => 0.01,
105 STARTUP_WAIT => false,
106 CLK0_VCODIV => sys_conf_clksys_vcodivide,
107 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
108 CLK0_OUTDIV => sys_conf_clksys_outdivide,
109 CLK0_GENTYPE => sys_conf_clksys_gentype,
110 CLK0_CDUWIDTH => 8,
111 CLK0_USECDIV => sys_conf_clksys_mhz,
112 CLK0_MSECDIV => sys_conf_clksys_msecdiv,
113 CLK1_VCODIV => sys_conf_clkser_vcodivide,
114 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
115 CLK1_OUTDIV => sys_conf_clkser_outdivide,
116 CLK1_GENTYPE => sys_conf_clkser_gentype,
117 CLK1_CDUWIDTH => 7,
118 CLK1_USECDIV => sys_conf_clkser_mhz,
119 CLK1_MSECDIV => sys_conf_clkser_msecdiv)
120 port map (
121 CLKIN => I_CLK100,
122 CLK0 => CLK,
123 CE0_USEC => CE_USEC,
124 CE0_MSEC => CE_MSEC,
125 CLK1 => CLKS,
126 CE1_USEC => open,
127 CE1_MSEC => CES_MSEC,
128 LOCKED => open
129 );
130
131 HIO : sn_humanio
132 generic map (
133 SWIDTH => 16,
134 BWIDTH => 5,
135 LWIDTH => 16,
136 DCWIDTH => 3,
137 DEBOUNCE => sys_conf_hio_debounce)
138 port map (
139 CLK => CLK,
140 RESET => '0',
141 CE_MSEC => CE_MSEC,
142 SWI => SWI,
143 BTN => BTN,
144 LED => LED,
145 DSP_DAT => DSP_DAT,
146 DSP_DP => DSP_DP,
147 I_SWI => I_SWI,
148 I_BTN => I_BTN,
149 O_LED => O_LED,
150 O_ANO_N => O_ANO_N,
152 );
153
154 RESET <= BTN(0); -- BTN(0) will reset tester !!
155
156 HIOMAP : tst_serloop_hiomap
157 port map (
158 CLK => CLK,
159 RESET => RESET,
163 SWI => SWI(7 downto 0),
164 BTN => BTN(3 downto 0),
165 LED => LED(7 downto 0),
166 DSP_DAT => DSP_DAT(15 downto 0),
167 DSP_DP => DSP_DP(3 downto 0)
168 );
169
170 IOB_RS232 : bp_rs232_4line_iob
171 port map (
172 CLK => CLKS,
173 RXD => RXD,
174 TXD => TXD,
175 CTS_N => CTS_N,
176 RTS_N => RTS_N,
177 I_RXD => I_RXD,
178 O_TXD => O_TXD,
179 I_CTS_N => I_CTS_N,
181 );
182
183 SERPORT : serport_2clock2
184 generic map (
185 CDWIDTH => 12,
186 CDINIT => sys_conf_uart_cdinit,
187 RXFAWIDTH => 5,
188 TXFAWIDTH => 5)
189 port map (
190 CLKU => CLK,
191 RESET => RESET,
192 CLKS => CLKS,
194 ENAXON => HIO_CNTL.enaxon,
195 ENAESC => HIO_CNTL.enaesc,
196 RXDATA => RXDATA,
197 RXVAL => RXVAL,
198 RXHOLD => RXHOLD,
199 TXDATA => TXDATA,
200 TXENA => TXENA,
201 TXBUSY => TXBUSY,
202 MONI => SER_MONI,
203 RXSD => RXD,
204 TXSD => TXD,
205 RXRTS_N => RTS_N,
206 TXCTS_N => CTS_N
207 );
208
209 TESTER : tst_serloop
210 port map (
211 CLK => CLK,
212 RESET => RESET,
213 CE_MSEC => CE_MSEC,
217 RXDATA => RXDATA,
218 RXVAL => RXVAL,
219 RXHOLD => RXHOLD,
220 TXDATA => TXDATA,
221 TXENA => TXENA,
222 TXBUSY => TXBUSY
223 );
224
225 -- show autobauder clock divisor on msb of display
226 DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
227 DSP_DAT(19) <= '0';
228 DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
229 DSP_DP(7 downto 4) <= "0010";
230
231 -- setup unused outputs in nexys4
232 O_RGBLED0 <= (others=>'0');
233 O_RGBLED1 <= (others=>not I_BTNRST_N);
234
235end syn;
TXFAWIDTH natural := 5
CDWIDTH positive := 13
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
DCWIDTH positive := 2
Definition: sn_humanio.vhd:53
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
LWIDTH positive := 8
Definition: sn_humanio.vhd:52
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
SWIDTH positive := 8
Definition: sn_humanio.vhd:50
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv32 :=( others => '0') DSP_DAT
hio_cntl_type := hio_cntl_init HIO_CNTL
slv16 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv16 :=( others => '0') LED
slv8 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in TXBUSY slbit
Definition: tst_serloop.vhd:48
in RESET slbit
Definition: tst_serloop.vhd:37
in RXDATA slv8
Definition: tst_serloop.vhd:42
in SER_MONI serport_moni_type
Definition: tst_serloop.vhd:41
out TXDATA slv8
Definition: tst_serloop.vhd:45
in CLK slbit
Definition: tst_serloop.vhd:36
out HIO_STAT hio_stat_type
Definition: tst_serloop.vhd:40
out RXHOLD slbit
Definition: tst_serloop.vhd:44
in RXVAL slbit
Definition: tst_serloop.vhd:43
in HIO_CNTL hio_cntl_type
Definition: tst_serloop.vhd:39
out TXENA slbit
Definition: tst_serloop.vhd:46
in CE_MSEC slbit
Definition: tst_serloop.vhd:38