Package >> simlib

Procedures
	readwhite( L: inout line )
	readoct( L: inout line value: out std_logic_vector good: out boolean )
	readhex( L: inout line value: out std_logic_vector good: out boolean )
	readgen( L: inout line value: out std_logic_vector good: out boolean base: in integer 2 )
	readcomment( L: inout line , good: out boolean )
	readdotcomm( L: inout line name: out string good: out boolean )
	readword( L: inout line name: out string good: out boolean )
	readoptchar( L: inout line char: in character good: out boolean )
	readempty( L: inout line )
	testempty( L: inout line , good: out boolean )
	testempty_ea( L: inout line )
	read_ea( L: inout line , value: out integer )
	read_ea( L: inout line , value: out time )
	readint_ea( L: inout line value: out integer imin: in integer integer ' low imax: in integer integer ' high )
	read_ea( L: inout line , value: out std_logic )
	read_ea( L: inout line , value: out std_logic_vector )
	readoct_ea( L: inout line , value: out std_logic_vector )
	readhex_ea( L: inout line , value: out std_logic_vector )
	readgen_ea( L: inout line value: out std_logic_vector base: in integer 2 )
	readword_ea( L: inout line , name: out string )
	readtagval( L: inout line tag: in string match: out boolean val: out std_logic_vector good: out boolean base: in integer 2 )
	readtagval_ea( L: inout line tag: in string match: out boolean val: out std_logic_vector base: in integer 2 )
	readtagval( L: inout line tag: in string match: out boolean val: out std_logic good: out boolean )
	readtagval_ea( L: inout line tag: in string match: out boolean val: out std_logic )
	readtagval2( L: inout line tag: in string match: out boolean val1: out std_logic_vector val2: out std_logic_vector good: out boolean base: in integer 2 )
	readtagval2_ea( L: inout line tag: in string match: out boolean val1: out std_logic_vector val2: out std_logic_vector base: in integer 2 )
	writeoct( L: inout line value: in std_logic_vector justified: in side right field: in width 0 )
	writehex( L: inout line value: in std_logic_vector justified: in side right field: in width 0 )
	writegen( L: inout line value: in std_logic_vector justified: in side right field: in width 0 base: in integer 2 )
	writetimens( L: inout line t: in time field: in width 0 )
	writetimestamp( L: inout line , str: in string null_string )
	writetimestamp( L: inout line clkcyc: in integer str: in string null_string )
	writeoptint( L: inout line str: in string dat: in integer field: in width 0 )
	writetrace( str: in string )
	writetrace( str: in string , dat: in integer )
	writetrace( str: in string , dat: in slbit )
	writetrace( str: in string , dat: in slv )
	wait_nextstim( signal clk: in slbit constant clk_dsc: in clock_dsc constant cnt: in positive 1 )
	wait_nextmoni( signal clk: in slbit constant clk_dsc: in clock_dsc constant cnt: in positive 1 )
	wait_stim2moni( signal clk: in slbit ,constant clk_dsc: in clock_dsc )
	wait_untilsignal( signal clk: in slbit constant clk_dsc: in clock_dsc signal sig: in slbit constant val: in slbit variable cnt: out natural )
	simfifo_put( cnt: inout natural arr: inout simfifo_type din: in std_logic_vector val: in slbit ' 1 ' )
	simfifo_get( cnt: inout natural arr: inout simfifo_type dout: out std_logic_vector )
	simfifo_writetest( L: inout line cnt: inout natural arr: inout simfifo_type dat: in std_logic_vector )
	simfifo_dump( cnt: inout natural arr: inout simfifo_type str: in string null_string )

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std
std_logic_textio
textio
slvtypes	Package <slvtypes>

Components
simclk	<Entity simclk>
simclkv	<Entity simclkv>
simclkcnt	<Entity simclkcnt>
simbididly	<Entity simbididly>

Constants
null_char	character := character ' val ( 0 )
null_string	string ( 1 to 1 ) := ( others = > null_char )

Types
simfifo_type	array ( natural range <> , natural range <> ) of std_logic

Records
clock_dsc
period	Delay_length
hold	Delay_length
setup	Delay_length

Detailed Description

Definition at line 53 of file simlib.vhd.

Member Function/Procedure/Process Documentation

◆ readwhite()

readwhite	(		L inout line
	)

Procedure

Definition at line 58 of file simlib.vhd.

◆ readoct()

readoct	(	L inout line ,
		value out std_logic_vector ,
		good out boolean
	)

Procedure

Definition at line 61 of file simlib.vhd.

◆ readhex()

readhex	(	L inout line ,
		value out std_logic_vector ,
		good out boolean
	)

Procedure

Definition at line 66 of file simlib.vhd.

◆ readgen()

readgen	(	L inout line ,
		value out std_logic_vector ,
		good out boolean ,
		base in integer 2
	)

Procedure

Definition at line 71 of file simlib.vhd.

◆ readcomment()

readcomment	(	L inout line ,
		good out boolean
	)

Procedure

Definition at line 77 of file simlib.vhd.

◆ readdotcomm()

readdotcomm	(	L inout line ,
		name out string ,
		good out boolean
	)

Procedure

Definition at line 81 of file simlib.vhd.

◆ readword()

readword	(	L inout line ,
		name out string ,
		good out boolean
	)

Procedure

Definition at line 86 of file simlib.vhd.

◆ readoptchar()

readoptchar	(	L inout line ,
		char in character ,
		good out boolean
	)

Procedure

Definition at line 91 of file simlib.vhd.

◆ readempty()

readempty	(		L inout line
	)

Procedure

Definition at line 96 of file simlib.vhd.

◆ testempty()

testempty	(	L inout line ,
		good out boolean
	)

Procedure

Definition at line 99 of file simlib.vhd.

◆ testempty_ea()

testempty_ea	(		L inout line
	)

Procedure

Definition at line 103 of file simlib.vhd.

◆ read_ea() [1/4]

read_ea	(	L inout line ,
		value out integer
	)

Procedure

Definition at line 106 of file simlib.vhd.

◆ read_ea() [2/4]

read_ea	(	L inout line ,
		value out time
	)

Procedure

Definition at line 109 of file simlib.vhd.

◆ readint_ea()

readint_ea	(	L inout line ,
		value out integer ,
		imin in integer integer'low ,
		imax in integer integer'high
	)

Procedure

Definition at line 113 of file simlib.vhd.

◆ read_ea() [3/4]

read_ea	(	L inout line ,
		value out std_logic
	)

Procedure

Definition at line 119 of file simlib.vhd.

◆ read_ea() [4/4]

read_ea	(	L inout line ,
		value out std_logic_vector
	)

Procedure

Definition at line 122 of file simlib.vhd.

◆ readoct_ea()

readoct_ea	(	L inout line ,
		value out std_logic_vector
	)

Procedure

Definition at line 126 of file simlib.vhd.

◆ readhex_ea()

readhex_ea	(	L inout line ,
		value out std_logic_vector
	)

Procedure

Definition at line 130 of file simlib.vhd.

◆ readgen_ea()

readgen_ea	(	L inout line ,
		value out std_logic_vector ,
		base in integer 2
	)

Procedure

Definition at line 134 of file simlib.vhd.

◆ readword_ea()

readword_ea	(	L inout line ,
		name out string
	)

Procedure

Definition at line 139 of file simlib.vhd.

◆ readtagval() [1/2]

readtagval	(	L inout line ,
		tag in string ,
		match out boolean ,
		val out std_logic_vector ,
		good out boolean ,
		base in integer 2
	)

Procedure

Definition at line 143 of file simlib.vhd.

◆ readtagval_ea() [1/2]

readtagval_ea	(	L inout line ,
		tag in string ,
		match out boolean ,
		val out std_logic_vector ,
		base in integer 2
	)

Procedure

Definition at line 150 of file simlib.vhd.

◆ readtagval() [2/2]

readtagval	(	L inout line ,
		tag in string ,
		match out boolean ,
		val out std_logic ,
		good out boolean
	)

Procedure

Definition at line 157 of file simlib.vhd.

◆ readtagval_ea() [2/2]

readtagval_ea	(	L inout line ,
		tag in string ,
		match out boolean ,
		val out std_logic
	)

Procedure

Definition at line 163 of file simlib.vhd.

◆ readtagval2()

readtagval2	(	L inout line ,
		tag in string ,
		match out boolean ,
		val1 out std_logic_vector ,
		val2 out std_logic_vector ,
		good out boolean ,
		base in integer 2
	)

Procedure

Definition at line 169 of file simlib.vhd.

◆ readtagval2_ea()

readtagval2_ea	(	L inout line ,
		tag in string ,
		match out boolean ,
		val1 out std_logic_vector ,
		val2 out std_logic_vector ,
		base in integer 2
	)

Procedure

Definition at line 177 of file simlib.vhd.

◆ writeoct()

writeoct	(	L inout line ,
		value in std_logic_vector ,
		justified in side right ,
		field in width 0
	)

Procedure

Definition at line 185 of file simlib.vhd.

◆ writehex()

writehex	(	L inout line ,
		value in std_logic_vector ,
		justified in side right ,
		field in width 0
	)

Procedure

Definition at line 191 of file simlib.vhd.

◆ writegen()

writegen	(	L inout line ,
		value in std_logic_vector ,
		justified in side right ,
		field in width 0 ,
		base in integer 2
	)

Procedure

Definition at line 197 of file simlib.vhd.

◆ writetimens()

writetimens	(	L inout line ,
		t in time ,
		field in width 0
	)

Procedure

Definition at line 204 of file simlib.vhd.

◆ writetimestamp() [1/2]

writetimestamp	(	L inout line ,
		str in string null_string
	)

Procedure

Definition at line 209 of file simlib.vhd.

◆ writetimestamp() [2/2]

writetimestamp	(	L inout line ,
		clkcyc in integer ,
		str in string null_string
	)

Procedure

Definition at line 213 of file simlib.vhd.

◆ writeoptint()

writeoptint	(	L inout line ,
		str in string ,
		dat in integer ,
		field in width 0
	)

Procedure

Definition at line 218 of file simlib.vhd.

◆ writetrace() [1/4]

writetrace	(		str in string
	)

Procedure

Definition at line 224 of file simlib.vhd.

◆ writetrace() [2/4]

writetrace	(	str in string ,
		dat in integer
	)

Procedure

Definition at line 226 of file simlib.vhd.

◆ writetrace() [3/4]

writetrace	(	str in string ,
		dat in slbit
	)

Procedure

Definition at line 229 of file simlib.vhd.

◆ writetrace() [4/4]

writetrace	(	str in string ,
		dat in slv
	)

Procedure

Definition at line 232 of file simlib.vhd.

◆ wait_nextstim()

wait_nextstim	(	signal	clk in slbit ,
		constant	clk_dsc in clock_dsc ,
		constant	cnt in positive 1
	)

Procedure

Definition at line 242 of file simlib.vhd.

◆ wait_nextmoni()

wait_nextmoni	(	signal	clk in slbit ,
		constant	clk_dsc in clock_dsc ,
		constant	cnt in positive 1
	)

Procedure

Definition at line 247 of file simlib.vhd.

◆ wait_stim2moni()

wait_stim2moni	(	signal	clk in slbit ,
		constant	clk_dsc in clock_dsc
	)

Procedure

Definition at line 252 of file simlib.vhd.

◆ wait_untilsignal()

wait_untilsignal	(	signal	clk in slbit ,
		constant	clk_dsc in clock_dsc ,
		signal	sig in slbit ,
		constant	val in slbit ,
		variable	cnt out natural
	)

Procedure

Definition at line 256 of file simlib.vhd.

◆ simfifo_put()

simfifo_put	(	cnt inout natural ,
		arr inout simfifo_type ,
		din in std_logic_vector ,
		val in slbit ' 1 '
	)

Procedure

Definition at line 265 of file simlib.vhd.

◆ simfifo_get()

simfifo_get	(	cnt inout natural ,
		arr inout simfifo_type ,
		dout out std_logic_vector
	)

Procedure

Definition at line 271 of file simlib.vhd.

◆ simfifo_writetest()

simfifo_writetest	(	L inout line ,
		cnt inout natural ,
		arr inout simfifo_type ,
		dat in std_logic_vector
	)

Procedure

Definition at line 276 of file simlib.vhd.

◆ simfifo_dump()

simfifo_dump	(	cnt inout natural ,
		arr inout simfifo_type ,
		str in string null_string
	)

Procedure

Definition at line 282 of file simlib.vhd.

Member Data Documentation

◆ ieee

ieee

Library

Definition at line 45 of file simlib.vhd.

◆ std_logic_1164

std_logic_1164

use clause

Definition at line 46 of file simlib.vhd.

◆ numeric_std

numeric_std

use clause

Definition at line 47 of file simlib.vhd.

◆ std_logic_textio

std_logic_textio

use clause

Definition at line 48 of file simlib.vhd.

◆ textio

textio

use clause

Definition at line 49 of file simlib.vhd.

◆ slvtypes

slvtypes

use clause

Definition at line 51 of file simlib.vhd.

◆ null_char

null_char character := character ' val ( 0 )

Constant

Definition at line 55 of file simlib.vhd.

◆ null_string

null_string string ( 1 to 1 ) := ( others = > null_char )

Constant

Definition at line 56 of file simlib.vhd.

◆ clock_dsc

clock_dsc

Record

Definition at line 236 of file simlib.vhd.

◆ period

period Delay_length

Record

Definition at line 237 of file simlib.vhd.

◆ hold

hold Delay_length

Record

Definition at line 238 of file simlib.vhd.

◆ setup

setup Delay_length

Record

Definition at line 239 of file simlib.vhd.

◆ simfifo_type

simfifo_type array ( natural range <> , natural range <> ) of std_logic

Type

Definition at line 263 of file simlib.vhd.

◆ simclk

simclk

Component

Definition at line 289 of file simlib.vhd.

◆ simclkv

simclkv

Component

Definition at line 299 of file simlib.vhd.

◆ simclkcnt

simclkcnt

Component

Definition at line 309 of file simlib.vhd.

◆ simbididly

simbididly

Component

Definition at line 316 of file simlib.vhd.

The documentation for this design unit was generated from the following file:

vlib/simlib/simlib.vhd

Procedures

Libraries

Use Clauses

Components

Constants

Types

Records

Detailed Description

Member Function/Procedure/Process Documentation

◆ readwhite()

◆ readoct()

◆ readhex()

◆ readgen()

◆ readcomment()

◆ readdotcomm()

◆ readword()

◆ readoptchar()

◆ readempty()

◆ testempty()

◆ testempty_ea()

◆ read_ea() [1/4]

◆ read_ea() [2/4]

◆ readint_ea()

◆ read_ea() [3/4]

◆ read_ea() [4/4]

◆ readoct_ea()

◆ readhex_ea()

◆ readgen_ea()

◆ readword_ea()

◆ readtagval() [1/2]

◆ readtagval_ea() [1/2]

◆ readtagval() [2/2]

◆ readtagval_ea() [2/2]

◆ readtagval2()

◆ readtagval2_ea()

◆ writeoct()

◆ writehex()

◆ writegen()

◆ writetimens()

◆ writetimestamp() [1/2]

◆ writetimestamp() [2/2]

◆ writeoptint()

◆ writetrace() [1/4]

◆ writetrace() [2/4]

◆ writetrace() [3/4]

◆ writetrace() [4/4]

◆ wait_nextstim()

◆ wait_nextmoni()

◆ wait_stim2moni()

◆ wait_untilsignal()

◆ simfifo_put()

◆ simfifo_get()

◆ simfifo_writetest()

◆ simfifo_dump()

Member Data Documentation

◆ ieee

◆ std_logic_1164

◆ numeric_std

◆ std_logic_textio

◆ textio

◆ slvtypes

◆ null_char

◆ null_string

◆ clock_dsc

◆ period

◆ hold

◆ setup

◆ simfifo_type

◆ simclk

◆ simclkv

◆ simclkcnt

◆ simbididly