w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
sn_humanio.vhd
Go to the documentation of this file.
1-- $Id: sn_humanio.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sn_humanio - syn
7-- Description: BTN,SWI,LED and DSP handling for s3board, nexys, basys
8--
9-- Dependencies: xlib/iob_reg_o_gen
10-- bpgen/bp_swibtnled
11-- bpgen/sn_7segctl
12--
13-- Test bench: -
14--
15-- Target Devices: generic
16-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
17--
18-- Synthesized (xst):
19-- Date Rev ise Target flop lutl lutm slic t peri
20-- 2015-01-24 637 14.7 131013 xc6slx16-2 77 79 0 28 s 3.5 ns (n4)
21-- 2015-01-24 637 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns (n2)
22-- 2015-01-24 410 14.7 131013 xc6slx16-2 47 52 0 18 s 3.4 ns
23-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
24-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
25-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
26--
27-- Revision History:
28-- Date Rev Version Comment
29-- 2015-01-24 637 1.3 add SWIDTH,LWIDTH,DCWIDTH (for nexys4,basys3)
30-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
31-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
32-- 2011-07-02 387 1.1.2 use bp_swibtnled
33-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
34-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
35-- 2010-04-10 275 1.0 Initial version
36------------------------------------------------------------------------------
37--
38
39library ieee;
40use ieee.std_logic_1164.all;
41
42use work.slvtypes.all;
43use work.xlib.all;
44use work.bpgenlib.all;
45
46-- ----------------------------------------------------------------------------
47
48entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
49 generic (
50 SWIDTH : positive := 8; -- SWI port width
51 BWIDTH : positive := 4; -- BTN port width
52 LWIDTH : positive := 8; -- LED port width
53 DCWIDTH : positive := 2; -- digit counter width (2 or 3)
54 DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
55 port (
56 CLK : in slbit; -- clock
57 RESET : in slbit := '0'; -- reset
58 CE_MSEC : in slbit; -- 1 ms clock enable
59 SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
60 BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
61 LED : in slv(LWIDTH-1 downto 0); -- led data
62 DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
63 DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
64 I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
65 I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
66 O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
67 O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
68 O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
69 );
70end sn_humanio;
71
72architecture syn of sn_humanio is
73
74 signal N_ANO_N : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
75 signal N_SEG_N : slv8 := (others=>'0');
76
77begin
78
79 IOB_ANO_N : iob_reg_o_gen
80 generic map (DWIDTH => 2**DCWIDTH)
81 port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
82
83 IOB_SEG_N : iob_reg_o_gen
84 generic map (DWIDTH => 8)
85 port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
86
87 HIO : bp_swibtnled
88 generic map (
89 SWIDTH => SWIDTH,
90 BWIDTH => BWIDTH,
91 LWIDTH => LWIDTH,
92 DEBOUNCE => DEBOUNCE)
93 port map (
94 CLK => CLK,
95 RESET => RESET,
96 CE_MSEC => CE_MSEC,
97 SWI => SWI,
98 BTN => BTN,
99 LED => LED,
100 I_SWI => I_SWI,
101 I_BTN => I_BTN,
102 O_LED => O_LED
103 );
104
105 DRV : sn_7segctl
106 generic map (
107 DCWIDTH => DCWIDTH,
108 CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
109 port map (
110 CLK => CLK,
111 DIN => DSP_DAT,
112 DP => DSP_DP,
113 ANO_N => N_ANO_N,
114 SEG_N => N_SEG_N
115 );
116
117end syn;
bp_swibtnled
Definition: bp_swibtnled.vhd:34
bp_swibtnled.DEBOUNCE
DEBOUNCE boolean := true
Definition: bp_swibtnled.vhd:39
bp_swibtnled.SWIDTH
SWIDTH positive := 4
Definition: bp_swibtnled.vhd:36
bp_swibtnled.O_LED
out O_LED slv( LWIDTH- 1 downto 0)
Definition: bp_swibtnled.vhd:50
bp_swibtnled.SWI
out SWI slv( SWIDTH- 1 downto 0)
Definition: bp_swibtnled.vhd:44
bp_swibtnled.I_BTN
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: bp_swibtnled.vhd:48
bp_swibtnled.LWIDTH
LWIDTH positive := 4
Definition: bp_swibtnled.vhd:38
bp_swibtnled.I_SWI
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: bp_swibtnled.vhd:47
bp_swibtnled.BTN
out BTN slv( BWIDTH- 1 downto 0)
Definition: bp_swibtnled.vhd:45
bp_swibtnled.CLK
in CLK slbit
Definition: bp_swibtnled.vhd:41
bp_swibtnled.BWIDTH
BWIDTH positive := 4
Definition: bp_swibtnled.vhd:37
bp_swibtnled.LED
in LED slv( LWIDTH- 1 downto 0)
Definition: bp_swibtnled.vhd:46
bp_swibtnled.RESET
in RESET slbit := '0'
Definition: bp_swibtnled.vhd:42
bp_swibtnled.CE_MSEC
in CE_MSEC slbit
Definition: bp_swibtnled.vhd:43
iob_reg_o_gen
Definition: iob_reg_o_gen.vhd:25
iob_reg_o_gen.CE
in CE slbit := '1'
Definition: iob_reg_o_gen.vhd:31
iob_reg_o_gen.PAD
out PAD slv( DWIDTH- 1 downto 0)
Definition: iob_reg_o_gen.vhd:34
iob_reg_o_gen.CLK
in CLK slbit
Definition: iob_reg_o_gen.vhd:30
iob_reg_o_gen.DO
in DO slv( DWIDTH- 1 downto 0)
Definition: iob_reg_o_gen.vhd:32
iob_reg_o_gen.DWIDTH
DWIDTH positive := 16
Definition: iob_reg_o_gen.vhd:27
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
slvtypes.slv
std_logic_vector slv
Definition: slvtypes.vhd:31
sn_7segctl
Definition: sn_7segctl.vhd:40
sn_7segctl.DIN
in DIN slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_7segctl.vhd:46
sn_7segctl.ANO_N
out ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_7segctl.vhd:48
sn_7segctl.DCWIDTH
DCWIDTH positive := 2
Definition: sn_7segctl.vhd:42
sn_7segctl.CLK
in CLK slbit
Definition: sn_7segctl.vhd:45
sn_7segctl.CDWIDTH
CDWIDTH positive := 6
Definition: sn_7segctl.vhd:43
sn_7segctl.SEG_N
out SEG_N slv8
Definition: sn_7segctl.vhd:50
sn_7segctl.DP
in DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_7segctl.vhd:47
sn_humanio.syn
Definition: sn_humanio.vhd:72
sn_humanio.syn.N_ANO_N
slv(( 2** DCWIDTH)- 1 downto 0) :=( others => '0') N_ANO_N
Definition: sn_humanio.vhd:74
sn_humanio.syn.N_SEG_N
slv8 :=( others => '0') N_SEG_N
Definition: sn_humanio.vhd:75
sn_humanio
Definition: sn_humanio.vhd:48
sn_humanio.DSP_DP
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
sn_humanio.DEBOUNCE
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
sn_humanio.O_LED
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
sn_humanio.DSP_DAT
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
sn_humanio.DCWIDTH
DCWIDTH positive := 2
Definition: sn_humanio.vhd:53
sn_humanio.SWI
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
sn_humanio.I_BTN
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
sn_humanio.LWIDTH
LWIDTH positive := 8
Definition: sn_humanio.vhd:52
sn_humanio.I_SWI
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
sn_humanio.O_SEG_N
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
sn_humanio.SWIDTH
SWIDTH positive := 8
Definition: sn_humanio.vhd:50
sn_humanio.BTN
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
sn_humanio.CLK
in CLK slbit
Definition: sn_humanio.vhd:56
sn_humanio.BWIDTH
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
sn_humanio.O_ANO_N
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
sn_humanio.LED
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
sn_humanio.RESET
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
sn_humanio.CE_MSEC
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
xlib
Definition: xlib.vhd:35