1 -- $Id: sys_tst_fx2loop_n2.vhd 649 2015-02-21 21:10:16Z mueller $
3 -- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
5 -- This program is free software; you may redistribute and/or modify it under
6 -- the terms of the GNU General Public License as published by the Free
7 -- Software Foundation, either version 2, or at your option any later version.
9 -- This program is distributed in the hope that it will be useful, but
10 -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
11 -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 -- for complete details.
14 ------------------------------------------------------------------------------
15 -- Module Name: sys_tst_fx2loop_n2 - syn
16 -- Description: test of Cypress EZ-USB FX2 controller
18 -- Dependencies: vlib/xlib/dcm_sfs
19 -- vlib/genlib/clkdivce
23 -- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
24 -- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
25 -- bplib/nxcramlib/nx_cram_dummy
29 -- Target Devices: generic
30 -- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
33 -- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
34 -- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100
35 -- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100
36 -- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100
39 -- Date Rev Version Comment
40 -- 2015-01-25 638 1.1.1 retire fx2_2fifoctl_as
41 -- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers
42 -- 2011-12-26 445 1.0 Initial version
43 ------------------------------------------------------------------------------
46 use ieee.std_logic_1164.
all;
58 -- ----------------------------------------------------------------------------
61 -- implements nexys2_aif + fx2 pins
64 I_RXD : in slbit;
-- receive data (board view)
65 O_TXD : out slbit;
-- transmit data (board view)
69 O_ANO_N : out slv4;
-- 7 segment disp: anodes (act.low)
70 O_SEG_N : out slv8;
-- 7 segment disp: segments (act.low)
77 O_MEM_CRE : out slbit;
-- cram: command register enable
91 end sys_tst_fx2loop_n2;
95 signal CLK : slbit := '0';
101 signal SWI : slv8 := (others=>'0');
102 signal BTN : slv4 := (others=>'0');
103 signal LED : slv8 := (others=>'0');
124 signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
128 assert (sys_conf_clksys mod 1000000) = 0
129 report "assert sys_conf_clksys on MHz grid"
145 CDUWIDTH =>
7,
-- good for up to 127 MHz !
146 USECDIV => sys_conf_clksys_mhz ,
173 RESET <= BTN(0);
-- BTN(0) will reset tester !!
228 FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
234 CCWIDTH => sys_conf_fx2_ccwidth ,
258 end generate FX2_CNTL_IC;
260 FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
266 CCWIDTH => sys_conf_fx2_ccwidth ,
295 end generate FX2_CNTL_IC3;
311 O_FLA_CE_N <= '1';
-- keep Flash memory disabled
313 O_TXD <= I_RXD;
-- loop-back in serial port...
in FX2_MONIfx2ctl_moni_type
out HIO_STAThio_stat_type
slv4 :=( others =>'0' ) DSP_DP
slv8 :=( others =>'0' ) LED_MAP
TX2AFULL_THRESnatural :=1
nx_cram_dummy sram_protsram_prot
slv8 :=( others =>'0' ) SWI
out O_LEDslv (LWIDTH - 1 downto 0)
out HIO_CNTLhio_cntl_type
slv8 :=( others =>'0' ) FX2_TX2DATA
slv8 :=( others =>'0' ) LED
in DSP_DPslv ((2 ** DCWIDTH) - 1 downto 0)
out SWIslv (SWIDTH - 1 downto 0)
hio_stat_type :=hio_stat_init HIO_STAT
in I_SWIslv (SWIDTH - 1 downto 0)
in I_BTNslv (BWIDTH - 1 downto 0)
slv8 :=( others =>'0' ) FX2_TXDATA
in FX2_MONIfx2ctl_moni_type
proc_ledSWI,LED_MAP,FX2_TX2BUSY,FX2_TX2ENA,FX2_TXBUSY,FX2_TXENA,FX2_RXHOLD,FX2_RXVAL
RXAEMPTY_THRESnatural :=1
in DSP_DATslv (4 * (2 ** DCWIDTH) - 1 downto 0)
in LEDslv (LWIDTH - 1 downto 0)
out BTNslv (BWIDTH - 1 downto 0)
RXAEMPTY_THRESnatural :=1
slv16 :=( others =>'0' ) DSP_DAT
fx2ctl_moni_type :=fx2ctl_moni_init FX2_MONI
tst_fx2loop_hiomap hiomaphiomap
out O_ANO_Nslv ((2 ** DCWIDTH) - 1 downto 0)
slv8 :=( others =>'0' ) FX2_RXDATA
CLKFX_MULTIPLYpositive :=1
slv4 :=( others =>'0' ) BTN
hio_cntl_type :=hio_cntl_init HIO_CNTL