w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
rb_mon.vhd
Go to the documentation of this file.
1-- $Id: rb_mon.vhd 1203 2019-08-19 21:41:03Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rb_mon - sim
7-- Description: rbus monitor (for tb's)
8--
9-- Dependencies: -
10-- Test bench: -
11-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.36
12--
13-- Revision History:
14-- Date Rev Version Comment
15-- 2019-08-17 1203 4.1.2 fix for ghdl V0.36 -Whide warnings
16-- 2014-10-25 599 4.1.1 use writeoptint()
17-- 2014-09-03 591 4.1 add burst counter; add state checker
18-- 2014-08-30 589 4.0 use hex for addr; 4 bit STAT; monitor ACK=0
19-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
20-- 2011-12-23 444 3.1 CLK_CYCLE now integer
21-- 2011-11-19 427 3.0.1 now numeric_std clean
22-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
23-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
24-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
25-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
26-- drop RP_IINT signal from interfaces
27-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
28-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits
29-- 2007-12-23 105 1.2 added AP_LAM display
30-- 2007-11-24 98 1.1 added RP_IINT support
31-- 2007-08-27 76 1.0 Initial version
32------------------------------------------------------------------------------
33
34library ieee;
35use ieee.std_logic_1164.all;
36use ieee.numeric_std.all;
37use ieee.std_logic_textio.all;
38use std.textio.all;
39
40use work.slvtypes.all;
41use work.simlib.all;
42use work.rblib.all;
43
44entity rb_mon is -- rbus monitor (for tb's)
45 generic (
46 DBASE : positive := 2); -- base for writing data values
47 port (
48 CLK : in slbit; -- clock
49 CLK_CYCLE : in integer := 0; -- clock cycle number
50 ENA : in slbit := '1'; -- enable monitor output
51 RB_MREQ : in rb_mreq_type; -- rbus: request
52 RB_SRES : in rb_sres_type; -- rbus: response
53 RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
54 RB_STAT : in slv4 -- rbus: status flags
55 );
56end rb_mon;
57
58
59architecture sim of rb_mon is
60
61begin
62
63 proc_moni: process
64 variable oline : line;
65 variable nhold : integer := 0;
66 variable nburst : integer := 0;
67 variable data : slv16 := (others=>'0');
68 variable tag : string(1 to 8) := (others=>' ');
69 variable err : slbit := '0';
70 variable r_sel : slbit := '0';
71
72" " procedure write_data(L: inout line;
73 ptag: in string;
74 pdata: in slv16;
75 pnhold: in integer := 0;
76 pnburst: in integer := 0;
77 pcond: in boolean := false;
78 pctxt: in string := ) is
79 begin
80 writetimestamp(L, CLK_CYCLE, ptag);
81 writehex(L, RB_MREQ.addr, right, 4);
82 write(L, string'(" "));
83 writegen(L, pdata, right, 0, DBASE);
84 write(L, string'(" "));
85 write(L, RB_STAT, right, 4);
86 writeoptint(L, " hold=", pnhold, 2);
87 writeoptint(L, " b=", pnburst, 2);
88 if pcond then
89 write(L, pctxt);
90 end if;
91 writeline(output, L);
92 end procedure write_data;
93
94 begin
95
96 loop
97
98 if ENA = '0' then -- if disabled
99 wait until ENA='1'; -- stall process till enabled
100 end if;
101
102 wait until rising_edge(CLK); -- check at end of clock cycle
103
104 if RB_MREQ.aval='1' and r_sel='0' then
105 nburst := 0;
106 end if;
107
108 if RB_MREQ.re='1' or RB_MREQ.we='1' then
109 if RB_SRES.err = '1' then
110 err := '1';
111 end if;
112 if RB_SRES.busy = '1' then
113 nhold := nhold + 1;
114 else
115 data := (others=>'0');
116 tag := ": ???? ";
117 if RB_MREQ.re = '1' then
118 data := RB_SRES.dout;
119 tag := ": rbre ";
120 end if;
121 if RB_MREQ.we = '1' then
122 data := RB_MREQ.din;
123 tag := ": rbwe ";
124 end if;
125
126 if RB_SRES.ack = '1' then
127 write_data(oline, tag, data, nhold, nburst, err='1', " ERR='1'");
128 else
129 write_data(oline, tag, data, nhold, nburst, true, " ACK='0'");
130 end if;
131 nburst := nburst + 1;
132 nhold := 0;
133 end if;
134
135 else
136 if nhold > 0 then
137 write_data(oline, tag, data, nhold, nburst, true, " TIMEOUT");
138 end if;
139 nhold := 0;
140 err := '0';
141 end if;
142
143 if RB_MREQ.init = '1' then -- init
144 write_data(oline, ": rbini ", RB_MREQ.din);
145 end if;
146
147 if unsigned(RB_LAM) /= 0 then
148 write_data(oline, ": rblam ", RB_LAM, 0, 0, true, " RB_LAM active");
149 end if;
150
151 r_sel := RB_MREQ.aval;
152
153 end loop;
154 end process proc_moni;
155
156 proc_check: process (CLK)
157 variable r_sel : slbit := '0';
158 variable r_addr : slv16 := (others=>'0');
159 variable idump : boolean := false;
160 variable oline : line;
161 begin
162
163 if rising_edge(CLK) then
164 idump := false;
165
166 -- check that addr doesn't change after 1st aval cycle
167 if r_sel='1' and RB_MREQ.addr /= r_addr then
168 writetimestamp(oline, CLK_CYCLE,
169 ": FAIL rb_mon: addr changed after aval; initial addr=");
170 writehex(oline, r_addr, right, 4);
171 writeline(output, oline);
172 idump := true;
173 end if;
174
175 -- check that we,re don't come together in core select time
176 -- (aval and r_sel) and not at all outside
177 if RB_MREQ.aval='1' and r_sel='1' then
178 if RB_MREQ.we='1' and RB_MREQ.re='1' then
179 writetimestamp(oline, CLK_CYCLE,
180 ": FAIL rb_mon: we and re both active");
181 writeline(output, oline);
182 idump := true;
183 end if;
184 if RB_MREQ.init='1' then
185 writetimestamp(oline, CLK_CYCLE,
186 ": FAIL rb_mon: init seen inside select");
187 writeline(output, oline);
188 idump := true;
189 end if;
190 else
191 if RB_MREQ.we='1' or RB_MREQ.re='1' then
192 writetimestamp(oline, CLK_CYCLE,
193 ": FAIL rb_mon: no select and we,re seen");
194 writeline(output, oline);
195 idump := true;
196 end if;
197 end if;
198
199 -- check that init not seen when aval or select is active
200 if RB_MREQ.aval='1' or r_sel='1' then
201 if RB_MREQ.init='1' then
202 writetimestamp(oline, CLK_CYCLE,
203 ": FAIL rb_mon: init seen inside aval or select");
204 writeline(output, oline);
205 idump := true;
206 end if;
207 end if;
208
209 -- check that SRES isn't touched unless aval or select is active
210 if RB_MREQ.aval='0' and r_sel='0' then
211 if RB_SRES.dout/=x"0000" or RB_SRES.busy='1' or
212 RB_SRES.ack='1' or RB_SRES.err='1' then
213 writetimestamp(oline, CLK_CYCLE,
214 ": FAIL rb_mon: SRES driven outside aval or select");
215 writeline(output, oline);
216 idump := true;
217 end if;
218 end if;
219
220 -- dump rbus state in case of any error seen above
221 if idump then
222 write(oline, string'(" FAIL: MREQ aval="));
223 write(oline, RB_MREQ.aval, right, 1);
224 write(oline, string'(" re="));
225 write(oline, RB_MREQ.re , right, 1);
226 write(oline, string'(" we="));
227 write(oline, RB_MREQ.we , right, 1);
228 write(oline, string'(" init="));
229 write(oline, RB_MREQ.init, right, 1);
230 write(oline, string'(" sel="));
231 write(oline, r_sel , right, 1);
232 write(oline, string'(" addr="));
233 writehex(oline, RB_MREQ.addr, right, 4);
234 write(oline, string'(" din="));
235 writehex(oline, RB_MREQ.din, right, 4);
236 writeline(output, oline);
237
238 write(oline, string'(" FAIL: SRES ack="));
239 write(oline, RB_SRES.ack , right, 1);
240 write(oline, string'(" busy="));
241 write(oline, RB_SRES.busy, right, 1);
242 write(oline, string'(" err="));
243 write(oline, RB_SRES.err , right, 1);
244 write(oline, string'(" dout="));
245 writehex(oline, RB_SRES.dout, right, 4);
246 writeline(output, oline);
247 end if;
248
249 -- keep track of select state and latch current addr
250 if RB_MREQ.aval='1' and r_sel='0' then -- if 1st cycle of aval
251 r_addr := RB_MREQ.addr; -- latch addr
252 end if;
253 -- select simply aval if last cycle (assume all addr are valid)
254 r_sel := RB_MREQ.aval;
255 end if;
256
257 end process proc_check;
258
259end sim;
rb_mon.sim
Definition: rb_mon.vhd:59
rb_mon.sim.write_data
write_dataL,ptag,pdata,pnhold,pnburst,pcond,pctxt,
Definition: rb_mon.vhd:72
rb_mon
Definition: rb_mon.vhd:44
rb_mon.DBASE
DBASE positive := 2
Definition: rb_mon.vhd:46
rb_mon.CLK
in CLK slbit
Definition: rb_mon.vhd:48
rb_mon.RB_MREQ
in RB_MREQ rb_mreq_type
Definition: rb_mon.vhd:51
rb_mon.CLK_CYCLE
in CLK_CYCLE integer := 0
Definition: rb_mon.vhd:49
rb_mon.ENA
in ENA slbit := '1'
Definition: rb_mon.vhd:50
rb_mon.RB_STAT
in RB_STAT slv4
Definition: rb_mon.vhd:55
rb_mon.RB_LAM
in RB_LAM slv16 :=( others => '0')
Definition: rb_mon.vhd:53
rb_mon.RB_SRES
in RB_SRES rb_sres_type
Definition: rb_mon.vhd:52
rblib
Definition: rblib.vhd:32
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30