w11 - vhd 0.794
W11 CPU core and support modules
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rb_mon Entity Reference
Inheritance diagram for rb_mon:
[legend]

Entities

sim  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
std_logic_textio 
textio 
slvtypes  Package <slvtypes>
simlib  Package <simlib>
rblib  Package <rblib>

Generics

DBASE  positive := 2

Ports

CLK   in   slbit
CLK_CYCLE   in   integer := 0
ENA   in   slbit := ' 1 '
RB_MREQ   in   rb_mreq_type
RB_SRES   in   rb_sres_type
RB_LAM   in   slv16 := ( others = > ' 0 ' )
RB_STAT   in   slv4

Detailed Description

Definition at line 44 of file rb_mon.vhd.

Member Data Documentation

◆ DBASE

DBASE positive := 2
Generic

Definition at line 46 of file rb_mon.vhd.

◆ CLK

CLK in slbit
Port

Definition at line 48 of file rb_mon.vhd.

◆ CLK_CYCLE

CLK_CYCLE in integer := 0
Port

Definition at line 49 of file rb_mon.vhd.

◆ ENA

ENA in slbit := ' 1 '
Port

Definition at line 50 of file rb_mon.vhd.

◆ RB_MREQ

RB_MREQ in rb_mreq_type
Port

Definition at line 51 of file rb_mon.vhd.

◆ RB_SRES

RB_SRES in rb_sres_type
Port

Definition at line 52 of file rb_mon.vhd.

◆ RB_LAM

RB_LAM in slv16 := ( others = > ' 0 ' )
Port

Definition at line 53 of file rb_mon.vhd.

◆ RB_STAT

RB_STAT in slv4
Port

Definition at line 55 of file rb_mon.vhd.

◆ ieee

ieee
Library

Definition at line 34 of file rb_mon.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 35 of file rb_mon.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 36 of file rb_mon.vhd.

◆ std_logic_textio

std_logic_textio
use clause

Definition at line 37 of file rb_mon.vhd.

◆ textio

textio
use clause

Definition at line 38 of file rb_mon.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 40 of file rb_mon.vhd.

◆ simlib

simlib
use clause

Definition at line 41 of file rb_mon.vhd.

◆ rblib

rblib
use clause

Definition at line 42 of file rb_mon.vhd.


The documentation for this design unit was generated from the following file: