w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_tmu.vhd
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1-- $Id: pdp11_tmu.vhd 1348 2023-01-08 13:33:01Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2008-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_tmu - sim
7-- Description: pdp11: trace and monitor unit
8--
9-- Dependencies: -
10--
11-- Test bench: tb/tb_pdp11_core (implicit)
12-- Target Devices: generic
13-- Tool versions: viv 2016.2-2022.1; ghdl 0.18-2.0.0
14--
15-- Revision History:
16-- Date Rev Version Comment
17-- 2023-01-08 1348 1.3.3 add vm.vmcntl.[cm]acc, se.[iv]start fields
18-- 2022-10-25 1309 1.3.2 rename _gpr -> _gr
19-- 2018-10-05 1053 1.3.1 use DM_STAT_CA instead of DM_STAT_SY
20-- 2016-12-28 833 1.3 open tmu_ofile only when used
21-- 2015-07-03 697 1.2.1 adapt to new DM_STAT_SY/DM_STAT_VM
22-- 2015-05-03 674 1.2 start/stop/suspend overhaul
23-- 2011-12-23 444 1.1 use local clkcycle count instead of simbus global
24-- 2011-11-18 427 1.0.7 now numeric_std clean
25-- 2010-10-17 333 1.0.6 use ibus V2 interface
26-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
27-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
28-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
29-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
30-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
31-- 2008-04-19 137 1.0 Initial version
32------------------------------------------------------------------------------
33
34library ieee;
35use ieee.std_logic_1164.all;
36use ieee.numeric_std.all;
37use ieee.std_logic_textio.all;
38use std.textio.all;
39
40use work.slvtypes.all;
41use work.simlib.all;
42use work.simbus.all;
43use work.pdp11.all;
44
45-- ----------------------------------------------------------------------------
46
47entity pdp11_tmu is -- trace and monitor unit
48 port (
49 CLK : in slbit; -- clock
50 ENA : in slbit := '0'; -- enable trace output
51 DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
52 DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
53 DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
54 DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
55 DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
56 );
57end pdp11_tmu;
58
59
60architecture sim of pdp11_tmu is
61
62 signal R_FIRST : slbit := '1';
63
64begin
65
66 proc_tm: process (CLK)
67 variable oline : line;
68 variable clkcycle : integer := 0;
69 variable ipsw : slv16 := (others=>'0');
70 variable ibaddr : slv16 := (others=>'0');
71 variable emaddr : slv22 := (others=>'0');
72 variable dp_ireg_we_last : slbit := '0';
73 variable vm_ibsres_busy_last : slbit := '0';
74 variable vm_ibsres_ack_last : slbit := '0';
75 variable wcycle : boolean := false;
76 file ofile : text;
77 begin
78
79 if rising_edge(CLK) then
80
81 clkcycle := clkcycle + 1;
82
83 if ENA = '1' and R_FIRST = '1' then
84 -- open output file on first usage
85 file_open(ofile, "tmu_ofile", WRITE_MODE);
86 R_FIRST <= '0';
87
88 -- sequence of field desciptors must equal the sequence of writes later
89 write(oline, string'("#"));
90 write(oline, string'(" clkcycle:d"));
91 write(oline, string'(" cpu:o"));
92
93 write(oline, string'(" dp.pc:o"));
94 write(oline, string'(" dp.psw:o"));
95 write(oline, string'(" dp.ireg:o"));
96 write(oline, string'(" dp.ireg_we:b"));
97 write(oline, string'(" dp.ireg_we_last:b")); -- is ireg_we last cycle
98 write(oline, string'(" dp.dsrc:o"));
99 write(oline, string'(" dp.ddst:o"));
100 write(oline, string'(" dp.dtmp:o"));
101 write(oline, string'(" dp.dres:o"));
102 write(oline, string'(" dp.gr_adst:o"));
103 write(oline, string'(" dp.gr_mode:o"));
104 write(oline, string'(" dp.gr_bytop:b"));
105 write(oline, string'(" dp.gr_we:b"));
106
107 write(oline, string'(" se.istart:b"));
108 write(oline, string'(" se.vstart:b"));
109
110 write(oline, string'(" vm.vmcntl.cacc:b"));
111 write(oline, string'(" vm.vmcntl.macc:b"));
112 write(oline, string'(" vm.ibmreq.aval:b"));
113 write(oline, string'(" vm.ibmreq.re:b"));
114 write(oline, string'(" vm.ibmreq.we:b"));
115 write(oline, string'(" vm.ibmreq.rmw:b"));
116 write(oline, string'(" vm.ibmreq.be0:b"));
117 write(oline, string'(" vm.ibmreq.be1:b"));
118 write(oline, string'(" vm.ibmreq.cacc:b"));
119 write(oline, string'(" vm.ibmreq.racc:b"));
120 write(oline, string'(" vm.ibmreq.addr:o"));
121 write(oline, string'(" vm.ibmreq.din:o"));
122 write(oline, string'(" vm.ibsres.ack:b"));
123 write(oline, string'(" vm.ibsres.busy:b"));
124 write(oline, string'(" vm.ibsres.dout:o"));
125 write(oline, string'(" vm.emmreq.req:b"));
126 write(oline, string'(" vm.emmreq.we:b"));
127 write(oline, string'(" vm.emmreq.be:b"));
128 write(oline, string'(" vm.emmreq.cancel:b"));
129 write(oline, string'(" vm.emmreq.addr:o"));
130 write(oline, string'(" vm.emmreq.din:o"));
131 write(oline, string'(" vm.emsres.ack_r:b"));
132 write(oline, string'(" vm.emsres.ack_w:b"));
133 write(oline, string'(" vm.emsres.dout:o"));
134
135 write(oline, string'(" co.cpugo:b"));
136 write(oline, string'(" co.cpususp:b"));
137 write(oline, string'(" co.suspint:b"));
138 write(oline, string'(" co.suspext:b"));
139
140 write(oline, string'(" ca.rd:b"));
141 write(oline, string'(" ca.wr:b"));
142 write(oline, string'(" ca.rdhit:b"));
143 write(oline, string'(" ca.wrhit:b"));
144 write(oline, string'(" ca.rdmem:b"));
145 write(oline, string'(" ca.wrmem:b"));
146 write(oline, string'(" ca.rdwait:b"));
147 write(oline, string'(" ca.wrwait:b"));
148
149 writeline(ofile, oline);
150 end if;
151
152 ipsw := (others=>'0');
153 ipsw(psw_ibf_cmode) := DM_STAT_DP.psw.cmode;
154 ipsw(psw_ibf_pmode) := DM_STAT_DP.psw.pmode;
155 ipsw(psw_ibf_rset) := DM_STAT_DP.psw.rset;
156 ipsw(psw_ibf_pri) := DM_STAT_DP.psw.pri;
157 ipsw(psw_ibf_tflag) := DM_STAT_DP.psw.tflag;
158 ipsw(psw_ibf_cc) := DM_STAT_DP.psw.cc;
159
160 ibaddr := "1110000000000000";
161 ibaddr(DM_STAT_VM.ibmreq.addr'range) := DM_STAT_VM.ibmreq.addr;
162
163 emaddr := (others=>'0');
164 emaddr(DM_STAT_VM.emmreq.addr'range) := DM_STAT_VM.emmreq.addr;
165
166 wcycle := false;
167 if dp_ireg_we_last='1' or
168 DM_STAT_DP.gr_we='1' or
169 DM_STAT_VM.emmreq.req='1' or
170 DM_STAT_VM.emsres.ack_r='1' or
171 DM_STAT_VM.emsres.ack_w='1' or
172 DM_STAT_VM.emmreq.cancel='1' or
173 DM_STAT_VM.ibmreq.re='1' or
174 DM_STAT_VM.ibmreq.we='1' or
175 DM_STAT_VM.ibsres.ack='1'
176 then
177 wcycle := true;
178 end if;
179
180 if DM_STAT_VM.ibsres.busy='0' and
181 (vm_ibsres_busy_last='1' and vm_ibsres_ack_last='0')
182 then
183 wcycle := true;
184 end if;
185
186 if ENA = '0' then -- if not enabled
187 wcycle := false; -- force to not logged...
188 end if;
189
190 if wcycle then
191 -- sequence of writes must equal the sequence of field desciptors above
192 write(oline, clkcycle, right, 9);
193 write(oline, string'(" 0"));
194
195 writeoct(oline, DM_STAT_DP.pc, right, 7);
196 writeoct(oline, ipsw, right, 7);
197 writeoct(oline, DM_STAT_DP.ireg, right, 7);
198 write(oline, DM_STAT_DP.ireg_we, right, 2);
199 write(oline, dp_ireg_we_last, right, 2);
200 writeoct(oline, DM_STAT_DP.dsrc, right, 7);
201 writeoct(oline, DM_STAT_DP.ddst, right, 7);
202 writeoct(oline, DM_STAT_DP.dtmp, right, 7);
203 writeoct(oline, DM_STAT_DP.dres, right, 7);
204 writeoct(oline, DM_STAT_DP.gr_adst, right, 2);
205 writeoct(oline, DM_STAT_DP.gr_mode, right, 2);
206 write(oline, DM_STAT_DP.gr_bytop, right, 2);
207 write(oline, DM_STAT_DP.gr_we, right, 2);
208
209 write(oline, DM_STAT_SE.istart, right, 2);
210 write(oline, DM_STAT_SE.vstart, right, 2);
211
212 write(oline, DM_STAT_VM.vmcntl.cacc, right, 2);
213 write(oline, DM_STAT_VM.vmcntl.macc, right, 2);
214 write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
215 write(oline, DM_STAT_VM.ibmreq.re, right, 2);
216 write(oline, DM_STAT_VM.ibmreq.we, right, 2);
217 write(oline, DM_STAT_VM.ibmreq.rmw, right, 2);
218 write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
219 write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
220 write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
221 write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
222 writeoct(oline, ibaddr, right, 7);
223 writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
224 write(oline, DM_STAT_VM.ibsres.ack, right, 2);
225 write(oline, DM_STAT_VM.ibsres.busy, right, 2);
226 writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7);
227
228 write(oline, DM_STAT_VM.emmreq.req, right, 2);
229 write(oline, DM_STAT_VM.emmreq.we, right, 2);
230 write(oline, DM_STAT_VM.emmreq.be, right, 3);
231 write(oline, DM_STAT_VM.emmreq.cancel, right, 2);
232 writeoct(oline, emaddr, right, 9);
233 writeoct(oline, DM_STAT_VM.emmreq.din, right, 7);
234 write(oline, DM_STAT_VM.emsres.ack_r, right, 2);
235 write(oline, DM_STAT_VM.emsres.ack_w, right, 2);
236 writeoct(oline, DM_STAT_VM.emsres.dout, right, 7);
237
238 write(oline, DM_STAT_CO.cpugo, right, 2);
239 write(oline, DM_STAT_CO.cpususp, right, 2);
240 write(oline, DM_STAT_CO.suspint, right, 2);
241 write(oline, DM_STAT_CO.suspext, right, 2);
242
243 write(oline, DM_STAT_CA.rd, right, 2);
244 write(oline, DM_STAT_CA.wr, right, 2);
245 write(oline, DM_STAT_CA.rdhit, right, 2);
246 write(oline, DM_STAT_CA.wrhit, right, 2);
247 write(oline, DM_STAT_CA.rdmem, right, 2);
248 write(oline, DM_STAT_CA.wrmem, right, 2);
249 write(oline, DM_STAT_CA.rdwait, right, 2);
250 write(oline, DM_STAT_CA.wrwait, right, 2);
251
252 writeline(ofile, oline);
253 end if;
254
255 dp_ireg_we_last := DM_STAT_DP.ireg_we;
256 vm_ibsres_busy_last := DM_STAT_VM.ibsres.busy;
257 vm_ibsres_ack_last := DM_STAT_VM.ibsres.ack;
258
259 end if;
260
261 end process proc_tm;
262
263end sim;
pdp11_tmu.sim
Definition: pdp11_tmu.vhd:60
pdp11_tmu.sim.R_FIRST
slbit := '1' R_FIRST
Definition: pdp11_tmu.vhd:62
pdp11_tmu
Definition: pdp11_tmu.vhd:47
pdp11_tmu.DM_STAT_DP
in DM_STAT_DP dm_stat_dp_type
Definition: pdp11_tmu.vhd:51
pdp11_tmu.DM_STAT_CO
in DM_STAT_CO dm_stat_co_type
Definition: pdp11_tmu.vhd:54
pdp11_tmu.DM_STAT_SE
in DM_STAT_SE dm_stat_se_type
Definition: pdp11_tmu.vhd:52
pdp11_tmu.CLK
in CLK slbit
Definition: pdp11_tmu.vhd:49
pdp11_tmu.DM_STAT_VM
in DM_STAT_VM dm_stat_vm_type
Definition: pdp11_tmu.vhd:53
pdp11_tmu.ENA
in ENA slbit := '0'
Definition: pdp11_tmu.vhd:50
pdp11_tmu.DM_STAT_CA
in DM_STAT_CA dm_stat_ca_type
Definition: pdp11_tmu.vhd:56
pdp11
Definition: pdp11.vhd:123
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
slvtypes.slv22
std_logic_vector( 21 downto 0) slv22
Definition: slvtypes.vhd:55
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30