w11 - vhd 0.794
W11 CPU core and support modules
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simbus.vhd
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1-- $Id: simbus.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: simbus
7-- Description: Global signals for support control in test benches
8--
9-- Dependencies: -
10-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
11-- Revision History:
12-- Date Rev Version Comment
13-- 2016-09-02 805 2.1 rename SB_CLKSTOP > SB_SIMSTOP; init with 'L'
14-- 2011-12-23 444 2.0 remove global clock cycle signal SB_CLKCYCLE
15-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
16-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
17-- 2007-08-27 76 1.0 Initial version
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22
23use work.slvtypes.all;
24
25package simbus is
26
27 signal SB_SIMSTOP : slbit := 'L'; -- global simulation stop
28 signal SB_CNTL : slv16 := (others=>'L'); -- global signals tb -> uut
29 signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
30 signal SB_VAL : slbit := 'L'; -- init bcast valid
31 signal SB_ADDR : slv8 := (others=>'L'); -- init bcast address
32 signal SB_DATA : slv16 := (others=>'L'); -- init bcast data
33
34 -- Note: SB_SIMSTOP, SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak
35 -- ('L','H') and strong ('0','1') drivers. Therefore always remove
36 -- strenght before using, e.g. with to_x01()
37
38end package simbus;
slv16 :=( others => '0') SB_STAT
Definition: simbus.vhd:29
slv16 :=( others => 'L') SB_DATA
Definition: simbus.vhd:32
slv8 :=( others => 'L') SB_ADDR
Definition: simbus.vhd:31
slv16 :=( others => 'L') SB_CNTL
Definition: simbus.vhd:28
slbit := 'L' SB_VAL
Definition: simbus.vhd:30
slbit := 'L' SB_SIMSTOP
Definition: simbus.vhd:27
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40