simclkv Entity Reference

Inheritance diagram for simclkv:

Entities
sim	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std
slvtypes	Package <slvtypes>

Ports
CLK	out	slbit
CLK_PERIOD	in	Delay_length
CLK_HOLD	in	slbit := ' 0 '
CLK_STOP	in	slbit := ' 0 '

Detailed Description

Definition at line 27 of file simclkv.vhd.

Member Data Documentation

CLK

CLK out slbit

Port

Definition at line 30 of file simclkv.vhd.

CLK_PERIOD

CLK_PERIOD in Delay_length

Port

Definition at line 31 of file simclkv.vhd.

CLK_HOLD

CLK_HOLD in slbit := ' 0 '

Port

Definition at line 32 of file simclkv.vhd.

CLK_STOP

CLK_STOP in slbit := ' 0 '

Port

Definition at line 34 of file simclkv.vhd.

ieee

ieee

Library

Definition at line 22 of file simclkv.vhd.

std_logic_1164

std_logic_1164

use clause

Definition at line 23 of file simclkv.vhd.

numeric_std

numeric_std

use clause

Definition at line 24 of file simclkv.vhd.

slvtypes

slvtypes

use clause

Definition at line 25 of file simclkv.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/simlib/simclkv.vhd