w11 - vhd 0.791
W11 CPU core and support modules
sn_humanio_demu_rbus.vhd
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1-- $Id: sn_humanio_demu_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sn_humanio_demu_rbus - syn
7-- Description: sn_humanio_demu with rbus interceptor
8--
9-- Dependencies: bpgen/sn_humanio_demu
10--
11-- Test bench: -
12--
13-- Target Devices: generic
14-- Tool versions: xst 13.3-14.7; ghdl 0.0.29-0.35
15--
16-- Synthesized (xst):
17-- Date Rev ise Target flop lutl lutm slic t peri
18-- 2013-01-06 472 13.3 O76xd xc3s1000-4 160 136 0 124 s 6.1 ns
19--
20-- Revision History:
21-- Date Rev Version Comment
22-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
23-- 2013-01-06 472 1.0 Initial version (cloned from sn_humanio_rbus
24------------------------------------------------------------------------------
25--
26-- rbus registers:
27--
28-- Address Bits Name r/w/f Function
29-- bbbbbb00 cntl r/w/- Control register and BTN access
30-- x:08 btn r/w/- r: return hio BTN status
31-- w: ored with hio BTN to drive BTN
32-- 3 dsp_en r/w/- if 1 display data will be driven by rbus
33-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
34-- 1 led_en r/w/- if 1 LED will be driven by rri
35-- 0 swi_en r/w/- if 1 SWI will be driven by rri
36--
37-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
38-- w: will drive SWI when swi_en=1
39--
40-- bbbbbb10 led r/w/- Interface to LED and DSP_DP
41-- 15:12 dp r/w/- r: returns DSP_DP status
42-- w: will drive display dp's when dp_en=1
43-- 7:00 led r/w/- r: returns LED status
44-- w: will drive led's when led_en=1
45--
46-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status
47-- w: will drive DSP_DAT when dsp_en=1
48--
49
50library ieee;
51use ieee.std_logic_1164.all;
52use ieee.numeric_std.all;
53
54use work.slvtypes.all;
55use work.rblib.all;
56use work.bpgenlib.all;
57
58-- ----------------------------------------------------------------------------
59
60entity sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
61 generic (
62 DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
63 RB_ADDR : slv16 := x"fef0");
64 port (
65 CLK : in slbit; -- clock
66 RESET : in slbit := '0'; -- reset
67 CE_MSEC : in slbit; -- 1 ms clock enable
68 RB_MREQ : in rb_mreq_type; -- rbus: request
69 RB_SRES : out rb_sres_type; -- rbus: response
70 SWI : out slv8; -- switch settings, debounced
71 BTN : out slv4; -- button settings, debounced
72 LED : in slv8; -- led data
73 DSP_DAT : in slv16; -- display data
74 DSP_DP : in slv4; -- display decimal points
75 I_SWI : in slv8; -- pad-i: switches
76 I_BTN : in slv6; -- pad-i: buttons
77 O_LED : out slv8 -- pad-o: leds
78 );
80
81architecture syn of sn_humanio_demu_rbus is
82
83 type regs_type is record
84 rbsel : slbit; -- rbus select
85 swi : slv8; -- rbus swi
86 btn : slv4; -- rbus btn
87 led : slv8; -- rbus led
88 dsp_dat : slv16; -- rbus dsp_dat
89 dsp_dp : slv4; -- rbus dsp_dp
90 ledin : slv8; -- led from design
91 swieff : slv8; -- effective swi
92 btneff : slv4; -- effective btn
93 ledeff : slv8; -- effective led
94 dpeff : slv4; -- effective dsp_dp
95 dateff : slv16; -- effective dsp_dat
96 swi_en : slbit; -- enable: swi from rbus
97 led_en : slbit; -- enable: led from rbus
98 dsp_en : slbit; -- enable: dsp_dat from rbus
99 dp_en : slbit; -- enable: dsp_dp from rbus
100 end record regs_type;
101
102 constant regs_init : regs_type := (
103 '0', -- rbsel
104 (others=>'0'), -- swi
105 (others=>'0'), -- btn
106 (others=>'0'), -- led
107 (others=>'0'), -- dsp_dat
108 (others=>'0'), -- dsp_dp
109 (others=>'0'), -- ledin
110 (others=>'0'), -- swieff
111 (others=>'0'), -- btneff
112 (others=>'0'), -- ledeff
113 (others=>'0'), -- dpeff
114 (others=>'0'), -- dateff
115 '0','0','0','0' -- (swi|led|dsp|dp)_en
116 );
117
118 signal R_REGS : regs_type := regs_init; -- state registers
119 signal N_REGS : regs_type := regs_init; -- next value state regs
120
121 subtype cntl_rbf_btn is integer range 11 downto 8;
122 constant cntl_rbf_dsp_en: integer := 3;
123 constant cntl_rbf_dp_en: integer := 2;
124 constant cntl_rbf_led_en: integer := 1;
125 constant cntl_rbf_swi_en: integer := 0;
126 subtype led_rbf_dp is integer range 15 downto 12;
127 subtype led_rbf_led is integer range 7 downto 0;
128
129 constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/-
130 constant rbaddr_swi: slv2 := "01"; -- 1 r/w/-
131 constant rbaddr_led: slv2 := "10"; -- 2 r/w/-
132 constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/-
133
134 signal HIO_SWI : slv8 := (others=>'0');
135 signal HIO_BTN : slv4 := (others=>'0');
136 signal HIO_LED : slv8 := (others=>'0');
137 signal HIO_DSP_DAT : slv16 := (others=>'0');
138 signal HIO_DSP_DP : slv4 := (others=>'0');
139
140begin
141
142 HIO : sn_humanio_demu
143 generic map (
145 port map (
146 CLK => CLK,
147 RESET => RESET,
148 CE_MSEC => CE_MSEC,
149 SWI => HIO_SWI,
150 BTN => HIO_BTN,
151 LED => HIO_LED,
154 I_SWI => I_SWI,
155 I_BTN => I_BTN,
156 O_LED => O_LED
157 );
158
159 proc_regs: process (CLK)
160 begin
161
162 if rising_edge(CLK) then
163 if RESET = '1' then
164 R_REGS <= regs_init;
165 else
166 R_REGS <= N_REGS;
167 end if;
168 end if;
169
170 end process proc_regs;
171
172 proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
174
175 variable r : regs_type := regs_init;
176 variable n : regs_type := regs_init;
177
178 variable irb_ack : slbit := '0';
179 variable irb_busy : slbit := '0';
180 variable irb_err : slbit := '0';
181 variable irb_dout : slv16 := (others=>'0');
182 variable irbena : slbit := '0';
183
184 begin
185
186 r := R_REGS;
187 n := R_REGS;
188
189 irb_ack := '0';
190 irb_busy := '0';
191 irb_err := '0';
192 irb_dout := (others=>'0');
193
194 irbena := RB_MREQ.re or RB_MREQ.we;
195
196 -- input register for LED signal
197 n.ledin := LED;
198
199 -- rbus address decoder
200 n.rbsel := '0';
201 if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
202 n.rbsel := '1';
203 end if;
204
205 -- rbus transactions
206 if r.rbsel = '1' then
207 irb_ack := irbena; -- ack all accesses
208
209 case RB_MREQ.addr(1 downto 0) is
210
211 when rbaddr_cntl =>
212 irb_dout(cntl_rbf_btn) := HIO_BTN;
213 irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
214 irb_dout(cntl_rbf_dp_en) := r.dp_en;
215 irb_dout(cntl_rbf_led_en) := r.led_en;
216 irb_dout(cntl_rbf_swi_en) := r.swi_en;
217 if RB_MREQ.we = '1' then
218 n.btn := RB_MREQ.din(cntl_rbf_btn);
219 n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
220 n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
221 n.led_en := RB_MREQ.din(cntl_rbf_led_en);
222 n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
223 end if;
224
225 when rbaddr_swi =>
226 irb_dout(HIO_SWI'range) := HIO_SWI;
227 if RB_MREQ.we = '1' then
228 n.swi := RB_MREQ.din(n.swi'range);
229 end if;
230
231 when rbaddr_led =>
232 irb_dout(led_rbf_dp) := HIO_DSP_DP;
233 irb_dout(led_rbf_led) := r.ledin;
234 if RB_MREQ.we = '1' then
235 n.dsp_dp := RB_MREQ.din(led_rbf_dp);
236 n.led := RB_MREQ.din(led_rbf_led);
237 end if;
238
239 when rbaddr_dsp =>
240 irb_dout := HIO_DSP_DAT;
241 if RB_MREQ.we = '1' then
242 n.dsp_dat := RB_MREQ.din;
243 end if;
244
245 when others => null;
246 end case;
247
248 end if;
249
250 n.btneff := HIO_BTN or r.btn;
251
252 if r.swi_en = '0' then
253 n.swieff := HIO_SWI;
254 else
255 n.swieff := r.swi;
256 end if;
257
258 if r.led_en = '0' then
259 n.ledeff := r.ledin;
260 else
261 n.ledeff := r.led;
262 end if;
263
264 if r.dp_en = '0' then
265 n.dpeff := DSP_DP;
266 else
267 n.dpeff := r.dsp_dp;
268 end if;
269
270 if r.dsp_en = '0' then
271 n.dateff := DSP_DAT;
272 else
273 n.dateff := r.dsp_dat;
274 end if;
275
276 N_REGS <= n;
277
278 BTN <= R_REGS.btneff;
279 SWI <= R_REGS.swieff;
280 HIO_LED <= R_REGS.ledeff;
281 HIO_DSP_DP <= R_REGS.dpeff;
282 HIO_DSP_DAT <= R_REGS.dateff;
283
284 RB_SRES <= rb_sres_init;
285 RB_SRES.ack <= irb_ack;
286 RB_SRES.busy <= irb_busy;
287 RB_SRES.err <= irb_err;
288 RB_SRES.dout <= irb_dout;
289
290 end process proc_next;
291
292end syn;
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 5 downto 0) slv6
Definition: slvtypes.vhd:38
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slv4 :=( others => '0') HIO_DSP_DP
integer range 15 downto 12 led_rbf_dp
regs_type := regs_init N_REGS
integer range 11 downto 8 cntl_rbf_btn
slv8 :=( others => '0') HIO_LED
integer range 7 downto 0 led_rbf_led
regs_type :=( '0',( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'), '0', '0', '0', '0') regs_init
slv16 :=( others => '0') HIO_DSP_DAT
regs_type := regs_init R_REGS
slv8 :=( others => '0') HIO_SWI
slv4 :=( others => '0') HIO_BTN
out RB_SRES rb_sres_type
DEBOUNCE boolean := true
in RESET slbit := '0'