51use ieee.std_logic_1164.
all;
52use ieee.numeric_std.
all;
162 if rising_edge(CLK) then
170 end process proc_regs;
178 variable irb_ack : slbit := '0';
179 variable irb_busy : slbit := '0';
180 variable irb_err : slbit := '0';
181 variable irb_dout : slv16 := (others=>'0');
182 variable irbena : slbit := '0';
192 irb_dout := (others=>'0');
206 if r.rbsel = '1' then
209 case RB_MREQ.addr(1 downto 0) is
228 n.swi := RB_MREQ.din(n.swi'range);
252 if r.swi_en = '0' then
258 if r.led_en = '0' then
264 if r.dp_en = '0' then
270 if r.dsp_en = '0' then
273 n.dateff := r.dsp_dat;
290 end process proc_next;
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 5 downto 0) slv6
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
integer := 1 cntl_rbf_led_en
integer := 3 cntl_rbf_dsp_en
slv4 :=( others => '0') HIO_DSP_DP
integer := 2 cntl_rbf_dp_en
integer range 15 downto 12 led_rbf_dp
regs_type := regs_init N_REGS
integer range 11 downto 8 cntl_rbf_btn
slv8 :=( others => '0') HIO_LED
integer range 7 downto 0 led_rbf_led
regs_type :=( '0',( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'), '0', '0', '0', '0') regs_init
slv16 :=( others => '0') HIO_DSP_DAT
regs_type := regs_init R_REGS
slv8 :=( others => '0') HIO_SWI
integer := 0 cntl_rbf_swi_en
slv4 :=( others => '0') HIO_BTN