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W11 CPU core and support modules
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rb_sres_or_mon.vhd
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1-- $Id: rb_sres_or_mon.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rb_sres_or_mon - sim
7-- Description: rbus result or monitor
8--
9-- Dependencies: -
10-- Test bench: -
11-- Tool versions: viv 2014.4-2015.4; ghdl 0.29-0.33
12--
13-- Revision History:
14-- Date Rev Version Comment
15-- 2016-03-13 743 3.1 now with 6 inputs; add RB_SRES_OR_MON_FAIL marker
16-- 2010-12-23 347 3.0 rename rritb_sres_or_mon->rb_sres_or_mon
17-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
18-- 2010-06-26 309 1.0 Initial version
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23use ieee.std_logic_textio.all;
24use std.textio.all;
25
26use work.slvtypes.all;
27use work.rblib.all;
28
29-- ----------------------------------------------------------------------------
30
31entity rb_sres_or_mon is -- rbus result or monitor
32 port (
33 RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
34 RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
35 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
36 RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
37 RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5
38 RB_SRES_6 : in rb_sres_type := rb_sres_init -- rb_sres input 6
39 );
40end rb_sres_or_mon;
41
42architecture sim of rb_sres_or_mon is
43
44 signal RB_SRES_OR_MON_FAIL : slbit := '0';
45
46begin
47
48 proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, RB_SRES_4)
49 constant dzero: slv16 := (others=>'0');
50 variable oline : line;
51 variable nack : integer := 0;
52 variable nbusy : integer := 0;
53 variable nerr : integer := 0;
54 variable ndout : integer := 0;
55 begin
56
57 nack := 0;
58 nbusy := 0;
59 nerr := 0;
60 ndout := 0;
61
62 if RB_SRES_1.ack /= '0' then nack := nack + 1; end if;
63 if RB_SRES_2.ack /= '0' then nack := nack + 1; end if;
64 if RB_SRES_3.ack /= '0' then nack := nack + 1; end if;
65 if RB_SRES_4.ack /= '0' then nack := nack + 1; end if;
66 if RB_SRES_5.ack /= '0' then nack := nack + 1; end if;
67 if RB_SRES_6.ack /= '0' then nack := nack + 1; end if;
68
69 if RB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
70 if RB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
71 if RB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
72 if RB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
73 if RB_SRES_5.busy /= '0' then nbusy := nbusy + 1; end if;
74 if RB_SRES_6.busy /= '0' then nbusy := nbusy + 1; end if;
75
76 if RB_SRES_1.err /= '0' then nerr := nerr + 1; end if;
77 if RB_SRES_2.err /= '0' then nerr := nerr + 1; end if;
78 if RB_SRES_3.err /= '0' then nerr := nerr + 1; end if;
79 if RB_SRES_4.err /= '0' then nerr := nerr + 1; end if;
80 if RB_SRES_5.err /= '0' then nerr := nerr + 1; end if;
81 if RB_SRES_6.err /= '0' then nerr := nerr + 1; end if;
82
83 if RB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
84 if RB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
85 if RB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
86 if RB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
87 if RB_SRES_5.dout /= dzero then ndout := ndout + 1; end if;
88 if RB_SRES_6.dout /= dzero then ndout := ndout + 1; end if;
89
90 RB_SRES_OR_MON_FAIL <= '0';
91 if now > 0 ns and (nack>1 or nbusy>1 or nerr>1 or ndout>1) then
92 RB_SRES_OR_MON_FAIL <= '1';
93 write(oline, now, right, 12);
94 if nack > 1 then
95 write(oline, string'(" #ack="));
96 write(oline, nack);
97 end if;
98 if nbusy > 1 then
99 write(oline, string'(" #busy="));
100 write(oline, nbusy);
101 end if;
102 if nerr > 1 then
103 write(oline, string'(" #err="));
104 write(oline, nerr);
105 end if;
106 if ndout > 1 then
107 write(oline, string'(" #dout="));
108 write(oline, ndout);
109 end if;
110 write(oline, string'(" FAIL in "));
111 write(oline, rb_sres_or_mon'path_name);
112 writeline(output, oline);
113 end if;
114
115 end process proc_comb;
116
117end sim;
rb_sres_or_mon.sim
Definition: rb_sres_or_mon.vhd:42
rb_sres_or_mon.sim.RB_SRES_OR_MON_FAIL
slbit := '0' RB_SRES_OR_MON_FAIL
Definition: rb_sres_or_mon.vhd:44
rb_sres_or_mon
Definition: rb_sres_or_mon.vhd:31
rb_sres_or_mon.RB_SRES_2
in RB_SRES_2 rb_sres_type
Definition: rb_sres_or_mon.vhd:34
rb_sres_or_mon.RB_SRES_3
in RB_SRES_3 rb_sres_type := rb_sres_init
Definition: rb_sres_or_mon.vhd:35
rb_sres_or_mon.RB_SRES_1
in RB_SRES_1 rb_sres_type
Definition: rb_sres_or_mon.vhd:33
rb_sres_or_mon.RB_SRES_4
in RB_SRES_4 rb_sres_type := rb_sres_init
Definition: rb_sres_or_mon.vhd:36
rb_sres_or_mon.RB_SRES_5
in RB_SRES_5 rb_sres_type := rb_sres_init
Definition: rb_sres_or_mon.vhd:37
rb_sres_or_mon.RB_SRES_6
in RB_SRES_6 rb_sres_type := rb_sres_init
Definition: rb_sres_or_mon.vhd:39
rblib
Definition: rblib.vhd:32
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30