w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_moni 
proc_simbus  ( SB_VAL )

Constants

sbaddr_portsel  slv8 := slv ( to_unsigned ( 8 , 8 ) )
clock_period  Delay_length := 10 ns
clock_offset  Delay_length := 200 ns

Signals

CLKOSC  slbit := ' 0 '
CLKCOM  slbit := ' 0 '
CLKCOM_CYCLE  integer := 0
RESET  slbit := ' 0 '
CLKDIV  slv2 := " 00 "
RXDATA  slv8 := ( others = > ' 0 ' )
RXVAL  slbit := ' 0 '
RXERR  slbit := ' 0 '
RXACT  slbit := ' 0 '
TXDATA  slv8 := ( others = > ' 0 ' )
TXENA  slbit := ' 0 '
TXBUSY  slbit := ' 0 '
I_RXD  slbit := ' 1 '
O_TXD  slbit := ' 1 '
I_SWI  slv4 := ( others = > ' 0 ' )
I_BTN  slv4 := ( others = > ' 0 ' )
O_LED  slv4 := ( others = > ' 0 ' )
O_RGBLED0  slv3 := ( others = > ' 0 ' )
O_RGBLED1  slv3 := ( others = > ' 0 ' )
O_RGBLED2  slv3 := ( others = > ' 0 ' )
O_RGBLED3  slv3 := ( others = > ' 0 ' )
IO_DDR3_DQ  slv16 := ( others = > ' Z ' )
IO_DDR3_DQS_P  slv2 := ( others = > ' Z ' )
IO_DDR3_DQS_N  slv2 := ( others = > ' Z ' )
R_PORTSEL_XON  slbit := ' 0 '

Instantiations

ginit  gsr_pulse <Entity gsr_pulse>
clkgen  simclk <Entity simclk>
clkgen_com  sfs_gsim_core <Entity sfs_gsim_core>
clkcnt  simclkcnt <Entity simclkcnt>
tbcore  tbcore_rlink <Entity tbcore_rlink>
artycore  tb_arty_core <Entity tb_arty_core>
uut  arty_dram_aif
sermstr  serport_master_tb <Entity serport_master_tb>

Detailed Description

Definition at line 45 of file tb_arty_dram.vhd.

Member Function/Procedure/Process Documentation

◆ proc_moni()

proc_moni

Definition at line 177 of file tb_arty_dram.vhd.

◆ proc_simbus()

proc_simbus (   SB_VAL  
)
Process

Definition at line 199 of file tb_arty_dram.vhd.

Member Data Documentation

◆ CLKOSC

CLKOSC slbit := ' 0 '
Signal

Definition at line 47 of file tb_arty_dram.vhd.

◆ CLKCOM

CLKCOM slbit := ' 0 '
Signal

Definition at line 48 of file tb_arty_dram.vhd.

◆ CLKCOM_CYCLE

CLKCOM_CYCLE integer := 0
Signal

Definition at line 50 of file tb_arty_dram.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 52 of file tb_arty_dram.vhd.

◆ CLKDIV

CLKDIV slv2 := " 00 "
Signal

Definition at line 53 of file tb_arty_dram.vhd.

◆ RXDATA

RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 54 of file tb_arty_dram.vhd.

◆ RXVAL

RXVAL slbit := ' 0 '
Signal

Definition at line 55 of file tb_arty_dram.vhd.

◆ RXERR

RXERR slbit := ' 0 '
Signal

Definition at line 56 of file tb_arty_dram.vhd.

◆ RXACT

RXACT slbit := ' 0 '
Signal

Definition at line 57 of file tb_arty_dram.vhd.

◆ TXDATA

TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 58 of file tb_arty_dram.vhd.

◆ TXENA

TXENA slbit := ' 0 '
Signal

Definition at line 59 of file tb_arty_dram.vhd.

◆ TXBUSY

TXBUSY slbit := ' 0 '
Signal

Definition at line 60 of file tb_arty_dram.vhd.

◆ I_RXD

I_RXD slbit := ' 1 '
Signal

Definition at line 62 of file tb_arty_dram.vhd.

◆ O_TXD

O_TXD slbit := ' 1 '
Signal

Definition at line 63 of file tb_arty_dram.vhd.

◆ I_SWI

I_SWI slv4 := ( others = > ' 0 ' )
Signal

Definition at line 64 of file tb_arty_dram.vhd.

◆ I_BTN

I_BTN slv4 := ( others = > ' 0 ' )
Signal

Definition at line 65 of file tb_arty_dram.vhd.

◆ O_LED

O_LED slv4 := ( others = > ' 0 ' )
Signal

Definition at line 66 of file tb_arty_dram.vhd.

◆ O_RGBLED0

O_RGBLED0 slv3 := ( others = > ' 0 ' )
Signal

Definition at line 67 of file tb_arty_dram.vhd.

◆ O_RGBLED1

O_RGBLED1 slv3 := ( others = > ' 0 ' )
Signal

Definition at line 68 of file tb_arty_dram.vhd.

◆ O_RGBLED2

O_RGBLED2 slv3 := ( others = > ' 0 ' )
Signal

Definition at line 69 of file tb_arty_dram.vhd.

◆ O_RGBLED3

O_RGBLED3 slv3 := ( others = > ' 0 ' )
Signal

Definition at line 70 of file tb_arty_dram.vhd.

◆ IO_DDR3_DQ

IO_DDR3_DQ slv16 := ( others = > ' Z ' )
Signal

Definition at line 72 of file tb_arty_dram.vhd.

◆ IO_DDR3_DQS_P

IO_DDR3_DQS_P slv2 := ( others = > ' Z ' )
Signal

Definition at line 73 of file tb_arty_dram.vhd.

◆ IO_DDR3_DQS_N

IO_DDR3_DQS_N slv2 := ( others = > ' Z ' )
Signal

Definition at line 74 of file tb_arty_dram.vhd.

◆ R_PORTSEL_XON

R_PORTSEL_XON slbit := ' 0 '
Signal

Definition at line 76 of file tb_arty_dram.vhd.

◆ sbaddr_portsel

sbaddr_portsel slv8 := slv ( to_unsigned ( 8 , 8 ) )
Constant

Definition at line 78 of file tb_arty_dram.vhd.

◆ clock_period

clock_period Delay_length := 10 ns
Constant

Definition at line 80 of file tb_arty_dram.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 81 of file tb_arty_dram.vhd.

◆ ginit

ginit gsr_pulse
Instantiation

Definition at line 85 of file tb_arty_dram.vhd.

◆ clkgen

clkgen simclk
Instantiation

Definition at line 93 of file tb_arty_dram.vhd.

◆ clkgen_com

clkgen_com sfs_gsim_core
Instantiation

Definition at line 104 of file tb_arty_dram.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 106 of file tb_arty_dram.vhd.

◆ tbcore

tbcore tbcore_rlink
Instantiation

Definition at line 116 of file tb_arty_dram.vhd.

◆ artycore

artycore tb_arty_core
Instantiation

Definition at line 122 of file tb_arty_dram.vhd.

◆ uut

uut arty_dram_aif
Instantiation

Definition at line 153 of file tb_arty_dram.vhd.

◆ sermstr

sermstr serport_master_tb
Instantiation

Definition at line 175 of file tb_arty_dram.vhd.

The documentation for this design unit was generated from the following file: