w11 - vhd 0.794
W11 CPU core and support modules
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Libraries | Ports | Use Clauses
tb_arty_core Entity Reference
Inheritance diagram for tb_arty_core:
[legend]

Entities

sim  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
std_logic_textio 
textio 
slvtypes  Package <slvtypes>
simbus  Package <simbus>

Ports

I_SWI   out   slv4
I_BTN   out   slv4

Detailed Description

Definition at line 29 of file tb_arty_core.vhd.

Member Data Documentation

◆ I_SWI

I_SWI out slv4
Port

Definition at line 31 of file tb_arty_core.vhd.

◆ I_BTN

I_BTN out slv4
Port

Definition at line 33 of file tb_arty_core.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file tb_arty_core.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 21 of file tb_arty_core.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 22 of file tb_arty_core.vhd.

◆ std_logic_textio

std_logic_textio
use clause

Definition at line 23 of file tb_arty_core.vhd.

◆ textio

textio
use clause

Definition at line 24 of file tb_arty_core.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 26 of file tb_arty_core.vhd.

◆ simbus

simbus
use clause

Definition at line 27 of file tb_arty_core.vhd.

The documentation for this design unit was generated from the following file: