w11 - vhd 0.794
W11 CPU core and support modules
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Generics | Libraries | Ports | Use Clauses
sysmonx_rbus_base Entity Reference
Inheritance diagram for sysmonx_rbus_base:
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Collaboration diagram for sysmonx_rbus_base:
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Entities

syn  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
numeric_std 
vcomponents 
slvtypes  Package <slvtypes>
rblib  Package <rblib>
sysmonrbuslib  Package <sysmonrbuslib>

Generics

INIT_TEMP_UP  real := 85 . 0
INIT_TEMP_LOW  real := 60 . 0
INIT_VCCINT_UP  real := 1 . 05
INIT_VCCINT_LOW  real := 0 . 95
INIT_VCCAUX_UP  real := 1 . 89
INIT_VCCAUX_LOW  real := 1 . 71
INIT_VCCBRAM_UP  real := 1 . 05
INIT_VCCBRAM_LOW  real := 0 . 95
CLK_MHZ  integer := 250
RB_ADDR  slv16 := x " fb00 "

Ports

CLK   in   slbit
RESET   in   slbit := ' 0 '
RB_MREQ   in   rb_mreq_type
RB_SRES   out   rb_sres_type
ALM   out   slv8
OT   out   slbit
TEMP   out   slv12

Detailed Description

Definition at line 41 of file sysmonx_rbus_base.vhd.

Member Data Documentation

◆ INIT_TEMP_UP

INIT_TEMP_UP real := 85 . 0
Generic

Definition at line 43 of file sysmonx_rbus_base.vhd.

◆ INIT_TEMP_LOW

INIT_TEMP_LOW real := 60 . 0
Generic

Definition at line 44 of file sysmonx_rbus_base.vhd.

◆ INIT_VCCINT_UP

INIT_VCCINT_UP real := 1 . 05
Generic

Definition at line 45 of file sysmonx_rbus_base.vhd.

◆ INIT_VCCINT_LOW

INIT_VCCINT_LOW real := 0 . 95
Generic

Definition at line 46 of file sysmonx_rbus_base.vhd.

◆ INIT_VCCAUX_UP

INIT_VCCAUX_UP real := 1 . 89
Generic

Definition at line 47 of file sysmonx_rbus_base.vhd.

◆ INIT_VCCAUX_LOW

INIT_VCCAUX_LOW real := 1 . 71
Generic

Definition at line 48 of file sysmonx_rbus_base.vhd.

◆ INIT_VCCBRAM_UP

INIT_VCCBRAM_UP real := 1 . 05
Generic

Definition at line 49 of file sysmonx_rbus_base.vhd.

◆ INIT_VCCBRAM_LOW

INIT_VCCBRAM_LOW real := 0 . 95
Generic

Definition at line 50 of file sysmonx_rbus_base.vhd.

◆ CLK_MHZ

CLK_MHZ integer := 250
Generic

Definition at line 51 of file sysmonx_rbus_base.vhd.

◆ RB_ADDR

RB_ADDR slv16 := x " fb00 "
Generic

Definition at line 52 of file sysmonx_rbus_base.vhd.

◆ CLK

CLK in slbit
Port

Definition at line 54 of file sysmonx_rbus_base.vhd.

◆ RESET

RESET in slbit := ' 0 '
Port

Definition at line 55 of file sysmonx_rbus_base.vhd.

◆ RB_MREQ

RB_MREQ in rb_mreq_type
Port

Definition at line 56 of file sysmonx_rbus_base.vhd.

◆ RB_SRES

RB_SRES out rb_sres_type
Port

Definition at line 57 of file sysmonx_rbus_base.vhd.

◆ ALM

ALM out slv8
Port

Definition at line 58 of file sysmonx_rbus_base.vhd.

◆ OT

OT out slbit
Port

Definition at line 59 of file sysmonx_rbus_base.vhd.

◆ TEMP

TEMP out slv12
Port

Definition at line 61 of file sysmonx_rbus_base.vhd.

◆ ieee

ieee
Library

Definition at line 28 of file sysmonx_rbus_base.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 29 of file sysmonx_rbus_base.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 30 of file sysmonx_rbus_base.vhd.

◆ unisim

unisim
Library

Definition at line 32 of file sysmonx_rbus_base.vhd.

◆ vcomponents

vcomponents
use clause

Definition at line 33 of file sysmonx_rbus_base.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 35 of file sysmonx_rbus_base.vhd.

◆ rblib

rblib
use clause

Definition at line 36 of file sysmonx_rbus_base.vhd.

◆ sysmonrbuslib

sysmonrbuslib
use clause

Definition at line 37 of file sysmonx_rbus_base.vhd.

The documentation for this design unit was generated from the following file: