w11 - vhd 0.794
W11 CPU core and support modules
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bp_swibtnled.vhd
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1-- $Id: bp_swibtnled.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: bp_swibtnled - syn
7-- Description: Generic SWI, BTN and LED handling
8--
9-- Dependencies: xlib/iob_reg_i_gen
10-- xlib/iob_reg_o_gen
11-- genlib/debounce_gen
12--
13-- Test bench: -
14--
15-- Target Devices: generic
16-- Tool versions: ise 11.4-14.7; viv 2014.4-2015.4; ghdl 0.26-0.33
17--
18-- Revision History:
19-- Date Rev Version Comment
20-- 2011-07-01 386 1.0 Initial version, extracted from s3_humanio
21------------------------------------------------------------------------------
22--
23
24library ieee;
25use ieee.std_logic_1164.all;
26
27use work.slvtypes.all;
28use work.xlib.all;
29use work.genlib.all;
30use work.bpgenlib.all;
31
32-- ----------------------------------------------------------------------------
33
34entity bp_swibtnled is -- generic SWI, BTN and LED handling
35 generic (
36 SWIDTH : positive := 4; -- SWI port width
37 BWIDTH : positive := 4; -- BTN port width
38 LWIDTH : positive := 4; -- LED port width
39 DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
40 port (
41 CLK : in slbit; -- clock
42 RESET : in slbit := '0'; -- reset
43 CE_MSEC : in slbit; -- 1 ms clock enable
44 SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
45 BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
46 LED : in slv(LWIDTH-1 downto 0); -- led data
47 I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
48 I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
49 O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
50 );
51end bp_swibtnled;
52
53architecture syn of bp_swibtnled is
54
55 signal RI_SWI : slv(SWIDTH-1 downto 0) := (others=>'0');
56 signal RI_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
57
58begin
59
60 IOB_SWI : iob_reg_i_gen
61 generic map (DWIDTH => SWIDTH)
62 port map (CLK => CLK, CE => '1', DI => RI_SWI, PAD => I_SWI);
63
64 IOB_BTN : iob_reg_i_gen
65 generic map (DWIDTH => BWIDTH)
66 port map (CLK => CLK, CE => '1', DI => RI_BTN, PAD => I_BTN);
67
68 IOB_LED : iob_reg_o_gen
69 generic map (DWIDTH => LWIDTH)
70 port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
71
72 DEB: if DEBOUNCE generate
73
74 DEB_SWI : debounce_gen
75 generic map (
76 CWIDTH => 2,
77 CEDIV => 3,
78 DWIDTH => SWIDTH)
79 port map (
80 CLK => CLK,
81 RESET => RESET,
82 CE_INT => CE_MSEC,
83 DI => RI_SWI,
84 DO => SWI
85 );
86
87 DEB_BTN : debounce_gen
88 generic map (
89 CWIDTH => 2,
90 CEDIV => 3,
91 DWIDTH => BWIDTH)
92 port map (
93 CLK => CLK,
94 RESET => RESET,
95 CE_INT => CE_MSEC,
96 DI => RI_BTN,
97 DO => BTN
98 );
99
100 end generate DEB;
101
102 NODEB: if not DEBOUNCE generate
103 SWI <= RI_SWI;
104 BTN <= RI_BTN;
105 end generate NODEB;
106
107end syn;
slv( BWIDTH- 1 downto 0) :=( others => '0') RI_BTN
slv( SWIDTH- 1 downto 0) :=( others => '0') RI_SWI
DEBOUNCE boolean := true
SWIDTH positive := 4
out O_LED slv( LWIDTH- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
LWIDTH positive := 4
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in CLK slbit
BWIDTH positive := 4
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'
in CE_MSEC slbit
DWIDTH positive := 8
in CE_INT slbit
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
CWIDTH positive := 2
in CLK slbit
CEDIV positive := 3
in RESET slbit := '0'
in CE slbit := '1'
in PAD slv( DWIDTH- 1 downto 0)
in CLK slbit
out DI slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in CE slbit := '1'
out PAD slv( DWIDTH- 1 downto 0)
in CLK slbit
in DO slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31
Definition: xlib.vhd:35