w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_sequencer.vhd
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1-- $Id: pdp11_sequencer.vhd 1349 2023-01-11 14:52:42Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2006-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_sequencer - syn
7-- Description: pdp11: CPU sequencer
8--
9-- Dependencies: ib_sel
10-- Test bench: tb/tb_pdp11_core (implicit)
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2023-01-11 1349 1.6.28 BUGFIX: handle CPUERR.rsv correctly
17-- 2023-01-02 1342 1.6.27 BUGFIX: cc state unchanged after abort
18-- 2022-12-26 1337 1.6.26 tbit logic overhaul 2, now fully 11/70 compatible
19-- 2022-12-12 1330 1.6.25 implement MMR0,MMR2 instruction complete
20-- 2022-12-10 1329 1.6.24 BUGFIX: get correct PS after vector push abort
21-- 2022-12-05 1324 1.6.23 tbit logic overhaul; use treq_tbit; cleanups
22-- use resetcnt for 8 cycle RESET wait
23-- 2022-11-29 1323 1.6.22 rename adderr -> oddadr, don't set after err_mmu
24-- 2022-11-28 1322 1.6.21 BUGFIX: correct mmu trap vs interrupt priority
25-- 2022-11-24 1321 1.6.20 BUGFIX: correct mmu trap handing in s_idecode
26-- 2022-11-21 1320 1.6.19 rename some rsv->ser and cpustat_type trap_->treq_;
27-- remove vm_cntl_type.trap_done;
28-- BUGFIX: correct ysv flow implementation
29-- 2022-11-18 1316 1.6.18 BUGFIX: use is_kstackdst1246 also in dstr flow
30-- 2022-10-29 1312 1.6.17 rename s_int_* -> s_vec_*, s_trap_* -> s_abort_*
31-- 2022-10-25 1309 1.6.16 rename _gpr -> _gr
32-- 2022-10-03 1301 1.6.15 finalize fix for I space mode=1 in s_dstr_def
33-- 2022-09-08 1296 1.6.14 BUGFIX: use I space for all mode=1,2,3 if reg=pc
34-- 2022-08-13 1279 1.6.13 ssr->mmr rename
35-- 2019-08-17 1203 1.6.12 fix for ghdl V0.36 -Whide warnings
36-- 2018-10-07 1054 1.6.11 drop ITIMER, use DM_STAT_SE.itimer
37-- 2018-10-06 1053 1.6.10 add DM_STAT_SE.(cpbusy,idec,pcload)
38-- 2017-04-23 885 1.6.9 not sys_conf_dmscnt: set SNUM from state category;
39-- change waitsusp logic; add WAIT to idm_idone
40-- 2016-12-27 831 1.6.8 CPUERR now cleared with creset
41-- 2016-10-03 812 1.6.7 always define DM_STAT_SE.snum
42-- 2016-05-26 768 1.6.6 don't init N_REGS (vivado fix for fsm inference)
43-- proc_snum conditional (vivado fsm workaround)
44-- 2015-08-02 708 1.6.5 BUGFIX: proper trap_mmu and trap_ysv handling
45-- 2015-08-01 707 1.6.4 set dm_idone in s_(trap_10|op_trap); add dm_vfetch
46-- 2015-07-19 702 1.6.3 add DM_STAT_SE, drop SNUM port
47-- 2015-07-10 700 1.6.2 use c_cpurust_hbpt
48-- 2015-06-26 695 1.6.1 add SNUM (state number) port
49-- 2015-05-10 678 1.6 start/stop/suspend overhaul; reset overhaul
50-- 2015-02-07 643 1.5.2 s_op_wait: load R0 in DSRC for DR emulation
51-- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit;
52-- use DP_STAT.div_quit; set munit_s_div_sr;
53-- BUGFIX: s_opg_div_sr: check for late div_quit
54-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
55-- 2011-11-18 427 1.4.2 now numeric_std clean
56-- 2010-10-23 335 1.4.1 use ib_sel
57-- 2010-10-17 333 1.4 use ibus V2 interface
58-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
59-- 2010-06-20 307 1.3.1 rename cpacc to cacc in vm_cntl_type
60-- 2010-06-13 305 1.3 remove CPDIN_WE, CPDOUT_WE out ports; set
61-- CNTL.cpdout_we instead of CPDOUT_WE
62-- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait
63-- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented)
64-- 2009-05-09 213 1.2.6 BUGFIX: use is_kstackdst1246, stklim for mode=6
65-- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode
66-- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling
67-- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug
68-- 2008-12-13 176 1.2.2 BUGFIX: use is_pci in s_dstw_inc if DSTDEF='1'
69-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc; prevent stale DSRC
70-- 2008-08-22 161 1.2 rename ubf_ -> ibf_; use iblib
71-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust; cp reset sets now
72-- c_cpurust_reset; proper c_cpurust_vfail handling
73-- 2008-04-27 140 1.1.8 BUGFIX: halt cpu in case of a vector fetch error
74-- use cpursta to encode why cpu halts, remove cpufail
75-- 2008-04-27 139 1.1.7 BUGFIX: correct bytop handling for address fetches;
76-- BUGFIX: redo mtp flow; add fork_dsta fork and ddst
77-- reload in s_opa_mtp_pop_w;
78-- 2008-04-19 137 1.1.6 BUGFIX: fix loop state in s_rti_getpc_w
79-- 2008-03-30 131 1.1.5 BUGFIX: inc/dec by 2 for byte mode -(sp),(sp)+
80-- inc/dec by 2 for @(R)+ and @-(R) also for bytop's
81-- 2008-03-02 121 1.1.4 remove snoopers; add waitsusp, redo WAIT handling
82-- 2008-02-24 119 1.1.3 add lah,rps,wps command; revamp cp memory access
83-- change WAIT logic, now also bails out on cp command
84-- 2008-01-20 112 1.1.2 rename PRESET->BRESET
85-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
86-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
87-- 2007-06-14 56 1.0.1 Use slvtypes.all
88-- 2007-05-12 26 1.0 Initial version
89------------------------------------------------------------------------------
90
91library ieee;
92use ieee.std_logic_1164.all;
93use ieee.numeric_std.all;
94
95use work.slvtypes.all;
96use work.iblib.all;
97use work.pdp11.all;
98use work.sys_conf.all;
99
100-- ----------------------------------------------------------------------------
101
102entity pdp11_sequencer is -- CPU sequencer
103 port (
104 CLK : in slbit; -- clock
105 GRESET : in slbit; -- general reset
106 PSW : in psw_type; -- processor status
107 IREG : in slv16; -- IREG
108 ID_STAT : in decode_stat_type; -- instr. decoder status
109 DP_STAT : in dpath_stat_type; -- data path status
110 CP_CNTL : in cp_cntl_type; -- console port control
111 VM_STAT : in vm_stat_type; -- virtual memory status port
112 INT_PRI : in slv3; -- interrupt priority
113 INT_VECT : in slv9_2; -- interrupt vector
114 INT_ACK : out slbit; -- interrupt acknowledge
115 CRESET : out slbit; -- cpu reset
116 BRESET : out slbit; -- bus reset
117 MMU_MONI : out mmu_moni_type; -- mmu monitor port
118 DP_CNTL : out dpath_cntl_type; -- data path control
119 VM_CNTL : out vm_cntl_type; -- virtual memory control port
120 CP_STAT : out cp_stat_type; -- console port status
121 ESUSP_O : out slbit; -- external suspend output
122 ESUSP_I : in slbit; -- external suspend input
123 HBPT : in slbit; -- hardware bpt
124 IB_MREQ : in ib_mreq_type; -- ibus request
125 IB_SRES : out ib_sres_type; -- ibus response
126 DM_STAT_SE : out dm_stat_se_type -- debug and monitor status - sequencer
127 );
128end pdp11_sequencer;
129
130architecture syn of pdp11_sequencer is
131
132 constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));
133
134 constant cpuerr_ibf_illhlt : integer := 7;
135 constant cpuerr_ibf_oddadr : integer := 6;
136 constant cpuerr_ibf_nxm : integer := 5;
137 constant cpuerr_ibf_iobto : integer := 4;
138 constant cpuerr_ibf_ysv : integer := 3;
139 constant cpuerr_ibf_rsv : integer := 2;
140
141 type state_type is (
142 s_idle,
143 s_cp_regread,
144 s_cp_rps,
145 s_cp_memr_w,
146 s_cp_memw_w,
147 s_ifetch,
148 s_ifetch_w,
149 s_idecode,
150
151 s_srcr_def,
152 s_srcr_def_w,
153 s_srcr_inc,
154 s_srcr_inc_w,
155 s_srcr_dec,
156 s_srcr_dec1,
157 s_srcr_ind,
158 s_srcr_ind1_w,
159 s_srcr_ind2,
160 s_srcr_ind2_w,
161
162 s_dstr_def,
163 s_dstr_def_w,
164 s_dstr_inc,
165 s_dstr_inc_w,
166 s_dstr_dec,
167 s_dstr_dec1,
168 s_dstr_ind,
169 s_dstr_ind1_w,
170 s_dstr_ind2,
171 s_dstr_ind2_w,
172
173 s_dstw_def,
174 s_dstw_def_w,
175 s_dstw_inc,
176 s_dstw_inc_w,
177 s_dstw_incdef_w,
178 s_dstw_dec,
179 s_dstw_dec1,
180 s_dstw_ind,
181 s_dstw_ind_w,
182 s_dstw_def246,
183
184 s_dsta_inc,
185 s_dsta_incdef_w,
186 s_dsta_dec,
187 s_dsta_dec1,
188 s_dsta_ind,
189 s_dsta_ind_w,
190
191 s_op_halt,
192 s_op_wait,
193 s_op_trap,
194 s_op_reset,
195 s_op_rts,
196 s_op_rts_pop,
197 s_op_rts_pop_w,
198 s_op_spl,
199 s_op_mcc,
200 s_op_br,
201 s_op_mark,
202 s_op_mark1,
203 s_op_mark_pop,
204 s_op_mark_pop_w,
205 s_op_sob,
206 s_op_sob1,
207
208 s_opg_gen,
209 s_opg_gen_rmw_w,
210 s_opg_mul,
211 s_opg_mul1,
212 s_opg_div,
213 s_opg_div_cn,
214 s_opg_div_cr,
215 s_opg_div_sq,
216 s_opg_div_sr,
217 s_opg_div_quit,
218 s_opg_ash,
219 s_opg_ash_cn,
220 s_opg_ashc,
221 s_opg_ashc_cn,
222 s_opg_ashc_wl,
223
224 s_opa_jsr,
225 s_opa_jsr1,
226 s_opa_jsr_push,
227 s_opa_jsr_push_w,
228 s_opa_jsr2,
229 s_opa_jmp,
230 s_opa_mtp,
231 s_opa_mtp_pop_w,
232 s_opa_mtp_reg,
233 s_opa_mtp_mem,
234 s_opa_mtp_mem_w,
235 s_opa_mfp_reg,
236 s_opa_mfp_mem,
237 s_opa_mfp_mem_w,
238 s_opa_mfp_dec,
239 s_opa_mfp_push,
240 s_opa_mfp_push_w,
241
242 s_abort_4,
243 s_abort_10,
244 s_trap_disp,
245
246 s_int_ext,
247
248 s_vec_getpc,
249 s_vec_getpc_w,
250 s_vec_getps,
251 s_vec_getps_w,
252 s_vec_getsp,
253 s_vec_decsp,
254 s_vec_pushps,
255 s_vec_pushps_w,
256 s_vec_pushpc,
257 s_vec_pushpc_w,
258
259 s_rti_getpc,
260 s_rti_getpc_w,
261 s_rti_getps,
262 s_rti_getps_w,
263 s_rti_newpc,
264
265 s_vmerr,
266 s_cpufail
267 );
268
269 signal R_STATE : state_type := s_idle;-- state register
270 signal N_STATE : state_type; -- don't init (vivado fix for fsm infer)
271
272 attribute fsm_encoding : string;
273 attribute fsm_encoding of R_STATE : signal is "one_hot";
274
275 signal R_STATUS : cpustat_type := cpustat_init;
276 signal N_STATUS : cpustat_type := cpustat_init;
277 signal R_CPUERR : cpuerr_type := cpuerr_init;
278 signal N_CPUERR : cpuerr_type := cpuerr_init;
279
280 signal R_IDSTAT : decode_stat_type := decode_stat_init;
281 signal N_IDSTAT : decode_stat_type := decode_stat_init;
282
283 signal R_VMSTAT : vm_stat_type := vm_stat_init;
284
285 signal IBSEL_CPUERR : slbit := '0';
286
287 signal VM_CNTL_L : vm_cntl_type := vm_cntl_init;
288
289begin
290
291 SEL : ib_sel
292 generic map (
293 IB_ADDR => ibaddr_cpuerr)
294 port map (
295 CLK => CLK,
296 IB_MREQ => IB_MREQ,
297 SEL => IBSEL_CPUERR
298 );
299
300 proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)
301 variable idout : slv16 := (others=>'0');
302 begin
303 idout := (others=>'0');
304 if IBSEL_CPUERR = '1' then
305 idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
306 idout(cpuerr_ibf_oddadr) := R_CPUERR.oddadr;
307 idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
308 idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
309 idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
310 idout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
311 end if;
312 IB_SRES.dout <= idout;
313 IB_SRES.ack <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all
314 IB_SRES.busy <= '0';
315 end process proc_ibres;
316
317 proc_status: process (CLK)
318 begin
319 if rising_edge(CLK) then
320 if GRESET = '1' then
321 R_STATUS <= cpustat_init;
322 R_IDSTAT <= decode_stat_init;
323 R_VMSTAT <= vm_stat_init;
324 else
325 R_STATUS <= N_STATUS;
326 R_IDSTAT <= N_IDSTAT;
327 R_VMSTAT <= VM_STAT;
328 end if;
329 end if;
330 end process proc_status;
331
332 -- ensure that CPUERR is reset with GRESET and CRESET
333 proc_cpuerr: process (CLK)
334 begin
335 if rising_edge(CLK) then
336 if GRESET = '1' or R_STATUS.creset = '1' then
337 R_CPUERR <= cpuerr_init;
338 else
339 R_CPUERR <= N_CPUERR;
340 end if;
341 end if;
342 end process proc_cpuerr;
343
344 proc_state: process (CLK)
345 begin
346 if rising_edge(CLK) then
347 if GRESET = '1' then
348 R_STATE <= s_idle;
349 else
350 R_STATE <= N_STATE;
351 end if;
352 end if;
353 end process proc_state;
354
355 proc_next: process (R_STATE, R_STATUS, PSW, CP_CNTL,
356 ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,
357 R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,
358 INT_PRI, INT_VECT, ESUSP_I, HBPT)
359
360 variable nstate : state_type;
361 variable nstatus : cpustat_type := cpustat_init;
362 variable ncpuerr : cpuerr_type := cpuerr_init;
363
364 variable ndpcntl : dpath_cntl_type := dpath_cntl_init;
365 variable nvmcntl : vm_cntl_type := vm_cntl_init;
366 variable nidstat : decode_stat_type := decode_stat_init;
367 variable nmmumoni : mmu_moni_type := mmu_moni_init;
368
369 variable imemok : boolean;
370 variable bytop : slbit := '0'; -- local bytop access flag
371 variable macc : slbit := '0'; -- local modify access flag
372
373 variable lvector : slv9_2 := (others=>'0'); -- local trap/interrupt vector
374
375 variable brcode : slv4 := (others=>'0'); -- reduced br opcode (15,10-8)
376 variable brcond : slbit := '0'; -- br condition value
377
378 variable is_kmode : slbit := '0'; -- cmode is kernel mode
379 variable is_kstackdst1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
380
381 variable int_pending : slbit := '0'; -- an interrupt is pending
382
383 variable idm_idle : slbit := '0'; -- idle for dm_stat_se
384 variable idm_cpbusy : slbit := '0'; -- cpbusy for dm_stat_se
385 variable idm_idec : slbit := '0'; -- idec for dm_stat_se
386 variable idm_idone : slbit := '0'; -- idone for dm_stat_se
387 variable idm_pcload : slbit := '0'; -- pcload for dm_stat_se
388
389 alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
390 alias SRCDEF : slbit is IREG(9); -- src register mode defered
391 alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
392 alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
393 alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
394 alias DSTDEF : slbit is IREG(3); -- dst register mode defered
395 alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
396
397 procedure do_memread_i(pnstate : inout state_type;
398 pndpcntl : inout dpath_cntl_type;
399 pnvmcntl : inout vm_cntl_type;
400 pwstate : in state_type) is
401 begin
402 pndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
403 pnvmcntl.dspace := '0';
404 pnvmcntl.req := '1';
405 pndpcntl.gr_pcinc := '1'; -- (pc)++
406 pnstate := pwstate;
407 end procedure do_memread_i;
408
409 procedure do_memread_d(pnstate : inout state_type;
410 pnvmcntl : inout vm_cntl_type;
411 pwstate : in state_type;
412 pbytop : in slbit := '0';
413 pmacc : in slbit := '0';
414 pispace : in slbit := '0';
415 pkstack : in slbit := '0') is
416 begin
417 pnvmcntl.dspace := not pispace;
418 pnvmcntl.bytop := pbytop;
419 pnvmcntl.macc := pmacc;
420 pnvmcntl.kstack := pkstack;
421 pnvmcntl.req := '1';
422 pnstate := pwstate;
423 end procedure do_memread_d;
424
425 procedure do_memread_srcinc(pnstate : inout state_type;
426 pndpcntl : inout dpath_cntl_type;
427 pnvmcntl : inout vm_cntl_type;
428 pwstate : in state_type;
429 pnmmumoni : inout mmu_moni_type;
430 pupdt_sp : in slbit := '0') is
431 begin
432 pndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
433 pndpcntl.ounit_const := "000000010"; -- OUNIT const=2
434 pndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
435 pndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
436 pndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
437 pndpcntl.dsrc_we := '1'; -- update DSRC
438 if pupdt_sp = '1' then
439 pnmmumoni.regmod := '1';
440 pnmmumoni.isdec := '0';
441 pndpcntl.gr_adst := c_gr_sp; -- update SP too
442 pndpcntl.gr_we := '1';
443 end if;
444 pndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
445 pnvmcntl.dspace := '1';
446 pnvmcntl.req := '1';
447 pnstate := pwstate;
448 end procedure do_memread_srcinc;
449
450 procedure do_memwrite(pnstate : inout state_type;
451 pnvmcntl : inout vm_cntl_type;
452 pwstate : in state_type;
453 pmacc : in slbit :='0';
454 pispace : in slbit := '0') is
455 begin
456 pnvmcntl.dspace := not pispace;
457 pnvmcntl.bytop := R_IDSTAT.is_bytop;
458 pnvmcntl.wacc := '1';
459 pnvmcntl.macc := pmacc;
460 pnvmcntl.req := '1';
461 pnstate := pwstate;
462 end procedure do_memwrite;
463
464 procedure do_memcheck(pnstate : inout state_type;
465 pnstatus : inout cpustat_type;
466 pmok : out boolean) is
467 begin
468 pnstate := pnstate; -- dummy to add driver (vivado)
469 pnstatus := pnstatus; -- "
470 pmok := false;
471 if VM_STAT.ack = '1' then
472 pmok := true;
473 if VM_STAT.trap_mmu = '1' then -- remember trap_mmu, may happen on any
474 pnstatus.treq_mmu := '1'; -- memory access of an instruction
475 end if;
476 if VM_STAT.trap_ysv = '1' then -- remember trap_ysv (on final writes)
477 if R_STATUS.in_vecysv = '0' then -- trap when not in ysv vector flow
478 pnstatus.treq_ysv := '1';
479 end if;
480 end if;
481 elsif VM_STAT.err='1' or VM_STAT.fail='1' then
482 pnstate := s_vmerr;
483 end if;
484 end procedure do_memcheck;
485
486 procedure do_const_opsize(pndpcntl : inout dpath_cntl_type;
487 pbytop : in slbit;
488 pisdef : in slbit;
489 pregnum : in slv3) is
490 begin
491 pndpcntl := pndpcntl; -- dummy to add driver (vivado)
492 if pbytop='0' or pisdef='1' or
493 pregnum=c_gr_pc or pregnum=c_gr_sp then
494 pndpcntl.ounit_const := "000000010";
495 else
496 pndpcntl.ounit_const := "000000001";
497 end if;
498 end procedure do_const_opsize;
499
500 procedure do_fork_dstr(pnstate : inout state_type;
501 pidstat : in decode_stat_type) is
502 begin
503 case pidstat.fork_dstr is
504 when c_fork_dstr_def => pnstate := s_dstr_def;
505 when c_fork_dstr_inc => pnstate := s_dstr_inc;
506 when c_fork_dstr_dec => pnstate := s_dstr_dec;
507 when c_fork_dstr_ind => pnstate := s_dstr_ind;
508 when others => pnstate := s_cpufail;
509 end case;
510 end procedure do_fork_dstr;
511
512 procedure do_fork_opg(pnstate : inout state_type;
513 pidstat : in decode_stat_type) is
514 begin
515 case pidstat.fork_opg is
516 when c_fork_opg_gen => pnstate := s_opg_gen;
517 when c_fork_opg_wdef => pnstate := s_dstw_def;
518 when c_fork_opg_winc => pnstate := s_dstw_inc;
519 when c_fork_opg_wdec => pnstate := s_dstw_dec;
520 when c_fork_opg_wind => pnstate := s_dstw_ind;
521 when c_fork_opg_mul => pnstate := s_opg_mul;
522 when c_fork_opg_div => pnstate := s_opg_div;
523 when c_fork_opg_ash => pnstate := s_opg_ash;
524 when c_fork_opg_ashc => pnstate := s_opg_ashc;
525 when others => pnstate := s_cpufail;
526 end case;
527 end procedure do_fork_opg;
528
529 procedure do_fork_opa(pnstate : inout state_type;
530 pidstat : in decode_stat_type) is
531 begin
532 case pidstat.fork_opa is
533 when c_fork_opa_jmp => pnstate := s_opa_jmp;
534 when c_fork_opa_jsr => pnstate := s_opa_jsr;
535 when c_fork_opa_mtp => pnstate := s_opa_mtp_mem;
536 when c_fork_opa_mfp_reg => pnstate := s_opa_mfp_reg;
537 when c_fork_opa_mfp_mem => pnstate := s_opa_mfp_mem;
538 when others => pnstate := s_cpufail;
539 end case;
540 end procedure do_fork_opa;
541
542 procedure do_fork_next(pnstate : inout state_type;
543 pnstatus : inout cpustat_type;
544 pnmmumoni : inout mmu_moni_type) is
545 begin
546 -- priority order
547 if pnstatus.treq_mmu='1' or -- mmu trap
548 pnstatus.treq_ysv='1' then -- ysv trap
549 pnstate := s_trap_disp;
550 elsif unsigned(INT_PRI) > unsigned(PSW.pri) then -- interrupts
551 pnstate := s_idle;
552 elsif pnstatus.treq_tbit='1' then -- tbit trap
553 pnstate := s_trap_disp;
554 elsif R_STATUS.cpugo='1' and -- running
555 R_STATUS.cpususp='0' and -- and not suspended
556 not R_STATUS.cmdbusy='1' then -- and no cmd pending
557 pnstate := s_ifetch; -- fetch next
558 else
559 pnstate := s_idle; -- otherwise idle
560 end if;
561 end procedure do_fork_next;
562
563 procedure do_fork_next_pref(pnstate : inout state_type;
564 pnstatus : inout cpustat_type;
565 pndpcntl : inout dpath_cntl_type;
566 pnvmcntl : inout vm_cntl_type;
567 pnmmumoni : inout mmu_moni_type) is
568 begin
569 pndpcntl := pndpcntl; -- dummy to add driver (vivado)
570 pnvmcntl := pnvmcntl; -- "
571 -- priority order
572 if pnstatus.treq_mmu='1' or -- mmu trap
573 pnstatus.treq_ysv='1' then -- ysv trap
574 pnstate := s_trap_disp;
575 elsif unsigned(INT_PRI) > unsigned(PSW.pri) then -- interrupts
576 pnstate := s_idle;
577 elsif pnstatus.treq_tbit='1' then -- tbit trap
578 pnstate := s_trap_disp;
579 elsif R_STATUS.cpugo='1' and -- running
580 R_STATUS.cpususp='0' and -- and not suspended
581 not R_STATUS.cmdbusy='1' then -- and no cmd pending
582 pnvmcntl.req := '1'; -- read next instruction
583 pndpcntl.gr_pcinc := '1' ; -- inc PC
584 pnmmumoni.istart := '1'; -- signal istart to MMU
585 pnstate := s_ifetch_w; -- next: wait for fetched instruction
586 else
587 pnstate := s_idle; -- otherwise idle
588 end if;
589 end procedure do_fork_next_pref;
590
591 procedure do_start_vec(pnstate : inout state_type;
592 pndpcntl : inout dpath_cntl_type;
593 pvector : in slv9_2) is
594 begin
595 pndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
596 pndpcntl.dtmp_we := not R_STATUS.in_vecflow; -- save PS on first entry
597 pndpcntl.ounit_azero := '1'; -- OUNIT A = 0
598 pndpcntl.ounit_const := pvector & "00"; -- vector
599 pndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)
600 pndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
601 pndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
602 pndpcntl.dsrc_we := '1'; -- DSRC = vector
603 pnstate := s_vec_getpc;
604 end procedure do_start_vec;
605
606 begin
607
608 nstate := R_STATE;
609 nstatus := R_STATUS;
610 ncpuerr := R_CPUERR;
611
612 nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait
613
614 -- itimer pulse logic:
615 -- if neither running nor suspended --> free run, set itimer = 1
616 -- otherwise clear to ensure single cycle pulses generated by
617 -- s_idecode or s_op_wait
618 if R_STATUS.cpugo='0' and R_STATUS.cpususp='0' then
619 nstatus.itimer := '1';
620 else
621 nstatus.itimer := '0';
622 end if;
623
624 nstatus.creset := '0'; -- ensure single cycle pulse
625 nstatus.breset := '0'; -- dito
626 nstatus.intack := '0'; -- dito
627
628 nidstat := R_IDSTAT;
629
630 if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !
631 ncpuerr := cpuerr_init;
632 end if;
633
634 int_pending := '0';
635 if unsigned(INT_PRI) > unsigned(PSW.pri) then
636 int_pending := '1';
637 end if;
638 nstatus.intpend := int_pending;
639
640 idm_idle := '0';
641 idm_cpbusy := '0';
642 idm_idec := '0';
643 idm_idone := '0';
644 idm_pcload := '0';
645
646 imemok := false;
647
648 nmmumoni := mmu_moni_init;
649 nmmumoni.vflow := R_STATUS.in_vecflow;
650
651 macc := '0';
652 bytop := '0';
653 brcode := IREG(15) & IREG(10 downto 8);
654 brcond := '1';
655
656 is_kmode := '0';
657 is_kstackdst1246 := '0';
658
659 if PSW.cmode = c_psw_kmode then
660 is_kmode := '1';
661 if DSTREG = c_gr_sp and
662 (DSTMODF="001" or DSTMODF="010" or
663 DSTMODF="100" or DSTMODF="110") then
664 is_kstackdst1246 := '1';
665 end if;
666 end if;
667
668 lvector := (others=>'0');
669
670 nvmcntl := vm_cntl_init;
671 nvmcntl.dspace := '1'; -- DEFAULT
672 nvmcntl.mode := PSW.cmode; -- DEFAULT
673 nvmcntl.vecser := R_STATUS.in_vecser; -- DEFAULT
674
675 ndpcntl := dpath_cntl_init;
676 ndpcntl.gr_asrc := SRCREG; -- DEFAULT
677 ndpcntl.gr_adst := DSTREG; -- DEFAULT
678 ndpcntl.gr_mode := PSW.cmode; -- DEFAULT
679 ndpcntl.gr_rset := PSW.rset; -- DEFAULT
680 ndpcntl.gr_we := '0'; -- DEFAULT
681 ndpcntl.gr_bytop := '0'; -- DEFAULT
682 ndpcntl.gr_pcinc := '0'; -- DEFAULT
683
684 ndpcntl.psr_ccwe := '0'; -- DEFAULT
685 ndpcntl.psr_we := '0'; -- DEFAULT
686 ndpcntl.psr_func := "000"; -- DEFAULT
687
688 ndpcntl.dsrc_sel := c_dpath_dsrc_src;
689 ndpcntl.dsrc_we := '0';
690 ndpcntl.ddst_sel := c_dpath_ddst_dst;
691 ndpcntl.ddst_we := '0';
692 ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
693 ndpcntl.dtmp_we := '0';
694
695 ndpcntl.ounit_asel := c_ounit_asel_ddst;
696 ndpcntl.ounit_azero := '0'; -- DEFAULT
697 ndpcntl.ounit_const := (others=>'0'); -- DEFAULT
698 ndpcntl.ounit_bsel := c_ounit_bsel_const;
699 ndpcntl.ounit_opsub := '0'; -- DEFAULT
700
701 ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC
702 ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC
703 ndpcntl.aunit_cimod := R_IDSTAT.aunit_cimod; -- STATIC
704 ndpcntl.aunit_cc1op := R_IDSTAT.aunit_cc1op; -- STATIC
705 ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC
706 ndpcntl.aunit_bytop := R_IDSTAT.is_bytop; -- STATIC
707
708 ndpcntl.lunit_func := R_IDSTAT.lunit_func; -- STATIC
709 ndpcntl.lunit_bytop := R_IDSTAT.is_bytop; -- STATIC
710
711 ndpcntl.munit_func := R_IDSTAT.munit_func; -- STATIC
712
713 ndpcntl.ireg_we := '0';
714
715 ndpcntl.cres_sel := R_IDSTAT.res_sel; -- DEFAULT
716 ndpcntl.dres_sel := c_dpath_res_ounit;
717 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;
718
719 if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then
720 nstatus.cmdbusy := '1';
721 nstatus.cpfunc := CP_CNTL.func;
722 nstatus.cprnum := CP_CNTL.rnum;
723 end if;
724
725 if R_STATUS.cmdack = '1' then
726 nstatus.cmdack := '0';
727 nstatus.cmderr := '0';
728 nstatus.cmdmerr := '0';
729 end if;
730
731 case R_STATE is
732
733 -- idle and command port states ---------------------------------------------
734
735 when s_idle => -- ------------------------------------
736 -- Note: s_idle was entered from suspended WAIT when waitsusp='1'
737 -- --> all exits must check this and either return to s_op_wait
738 -- or abort the WAIT and set waitsusp='0'
739
740 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST (do mux early)
741 nstatus.cpustep := '0';
742 idm_idle := '1'; -- signal sequencer idle
743
744 if R_STATUS.cmdbusy = '1' then
745 idm_cpbusy := '1'; -- signal cp busy
746 case R_STATUS.cpfunc is
747
748 when c_cpfunc_noop => -- noop : no operation -------
749 nstatus.cmdack := '1';
750 nstate := s_idle;
751
752 when c_cpfunc_start => -- start : cpu start ---------
753 nstatus.cmdack := '1';
754 if R_STATUS.cpugo = '1' then -- if already running
755 nstatus.cmderr := '1'; -- reject
756 else -- if not running
757 nstatus.cpugo := '1'; -- start cpu
758 nstatus.cpurust := c_cpurust_runs;
759 nstatus.waitsusp := '0';
760 end if;
761 nstate := s_idle;
762
763 when c_cpfunc_stop => -- stop : cpu stop -----------
764 nstatus.cmdack := '1';
765 nstatus.cpugo := '0';
766 nstatus.cpurust := c_cpurust_stop;
767 nstatus.waitsusp := '0';
768 nstate := s_idle;
769
770 when c_cpfunc_step => -- step : cpu step -----------
771 nstatus.cmdack := '1';
772 nstatus.cpustep := '1';
773 nstatus.cpurust := c_cpurust_step;
774 nstatus.waitsusp := '0';
775 if int_pending = '1' then
776 nstatus.intack := '1';
777 nstatus.intvect := INT_VECT;
778 nstate := s_int_ext;
779 else
780 nstate := s_ifetch;
781 end if;
782
783 when c_cpfunc_creset => -- creset : cpu reset --------
784 nstatus.cmdack := '1';
785 if R_STATUS.cpugo = '1' then -- if already running
786 nstatus.cmderr := '1'; -- reject
787 else -- if not running
788 nstatus.creset := '1'; -- do cpu reset
789 nstatus.breset := '1'; -- and bus reset !
790 nstatus.suspint := '0'; -- clear suspend
791 nstatus.treq_mmu := '0'; -- cancel trap requests
792 nstatus.treq_ysv := '0';
793 nstatus.treq_tbit := '0';
794 nstatus.in_vecflow := '0'; -- cancel in_* flags
795 nstatus.in_vecser := '0';
796 nstatus.in_vecysv := '0';
797 nstatus.cpurust := c_cpurust_init;
798 end if;
799 nstate := s_idle;
800
801 when c_cpfunc_breset => -- breset : bus reset --------
802 nstatus.cmdack := '1';
803 if R_STATUS.cpugo = '1' then -- if already running
804 nstatus.cmderr := '1'; -- reject
805 else -- if not running
806 nstatus.breset := '1'; -- do bus reset only
807 end if;
808 nstate := s_idle;
809
810 when c_cpfunc_suspend => -- suspend : cpu suspend -----
811 nstatus.cmdack := '1';
812 nstatus.suspint := '1';
813 nstatus.cpurust := c_cpurust_susp;
814 nstate := s_idle;
815
816 when c_cpfunc_resume => -- resume : cpu resume -------
817 nstatus.cmdack := '1';
818 nstatus.suspint := '0';
819 if R_STATUS.cpugo = '1' then
820 nstatus.cpurust := c_cpurust_runs;
821 else
822 nstatus.cpurust := c_cpurust_stop;
823 end if;
824 nstate := s_idle;
825
826 when c_cpfunc_rreg => -- rreg : read register ------
827 ndpcntl.gr_adst := R_STATUS.cprnum;
828 ndpcntl.ddst_sel := c_dpath_ddst_dst;
829 ndpcntl.ddst_we := '1';
830 nstate := s_cp_regread;
831
832 when c_cpfunc_wreg => -- wreg : write register -----
833 ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
834 ndpcntl.gr_adst := R_STATUS.cprnum;
835 ndpcntl.gr_we := '1';
836 nstatus.cmdack := '1';
837 nstate := s_idle;
838
839 when c_cpfunc_rpsw => -- rpsw : read psw -----------
840 ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
841 ndpcntl.dtmp_we := '1';
842 nstate := s_cp_rps;
843
844 when c_cpfunc_wpsw => -- wpsw : write psw ----------
845 ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
846 ndpcntl.psr_func := c_psr_func_wall; -- write all fields
847 ndpcntl.psr_we := '1'; -- load new PS
848 nstatus.cmdack := '1';
849 nstate := s_idle;
850
851 when c_cpfunc_rmem => -- rmem : read memory --------
852 nvmcntl.cacc := '1';
853 nvmcntl.req := '1';
854 nstate := s_cp_memr_w;
855
856 when c_cpfunc_wmem => -- wmem : write memory -------
857 ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
858 nvmcntl.wacc := '1'; -- write mem
859 nvmcntl.cacc := '1';
860 nvmcntl.req := '1';
861 nstate := s_cp_memw_w;
862
863 when others =>
864 nstatus.cmdack := '1';
865 nstatus.cmderr := '1';
866 nstate := s_idle;
867
868 end case;
869
870 elsif R_STATUS.waitsusp = '1' then
871 nstate := s_op_wait; --waitsusp is cleared in s_op_wait
872
873 elsif R_STATUS.cpugo = '1' and -- running
874 R_STATUS.cpususp='0' then -- and not suspended
875 -- proceed in priority order
876 if R_STATUS.treq_mmu='1' and -- mmu trap
877 R_STATUS.treq_ysv='1' then -- ysv trap
878 nstate := s_trap_disp;
879 elsif R_STATUS.intpend = '1' then -- interrupts
880 nstatus.intack := '1'; -- acknowledle it
881 nstatus.intvect := INT_VECT; -- latch vector address
882 nstate := s_int_ext; -- and handle
883 elsif R_STATUS.treq_tbit = '1' then -- tbit trap
884 nstate := s_trap_disp;
885 else
886 nstate := s_ifetch; -- otherwise fetch intruction
887 end if;
888 end if;
889
890 when s_cp_regread => -- -----------------------------------
891 idm_cpbusy := '1'; -- signal cp busy
892 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
893 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
894 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
895 nstatus.cmdack := '1';
896 nstate := s_idle;
897
898 when s_cp_rps => -- -----------------------------------
899 idm_cpbusy := '1'; -- signal cp busy
900 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
901 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
902 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
903 nstatus.cmdack := '1';
904 nstate := s_idle;
905
906 when s_cp_memr_w => -- -----------------------------------
907 idm_cpbusy := '1'; -- signal cp busy
908 nstate := s_cp_memr_w;
909 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
910 if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
911 nstatus.cmdack := '1';
912 nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
913 nstate := s_idle;
914 end if;
915
916 when s_cp_memw_w => -- -----------------------------------
917 idm_cpbusy := '1'; -- signal cp busy
918 nstate := s_cp_memw_w;
919 if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
920 nstatus.cmdack := '1';
921 nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
922 nstate := s_idle;
923 end if;
924
925 -- instruction fetch and decode ---------------------------------------------
926
927 when s_ifetch => -- -----------------------------------
928 nmmumoni.istart := '1'; -- do here; memread_i inc PC !
929 do_memread_i(nstate, ndpcntl, nvmcntl, s_ifetch_w);
930
931 when s_ifetch_w => -- -----------------------------------
932 nstate := s_ifetch_w;
933 do_memcheck(nstate, nstatus, imemok);
934 if imemok then
935 ndpcntl.ireg_we := '1';
936 nstate := s_idecode;
937 end if;
938
939 when s_idecode => -- -----------------------------------
940 idm_idec := '1'; -- signal instruction started
941 nstatus.itimer := '1'; -- itimer counts each decode
942 nidstat := ID_STAT; -- register decode status
943 if ID_STAT.force_srcsp = '1' then
944 ndpcntl.gr_asrc := c_gr_sp;
945 end if;
946 ndpcntl.dsrc_sel := c_dpath_dsrc_src;
947 ndpcntl.dsrc_we := '1';
948 ndpcntl.ddst_sel := c_dpath_ddst_dst;
949 ndpcntl.ddst_we := '1';
950
951 nvmcntl.dspace := '0';
952 ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
953
954 nstatus.resetcnt := "111"; -- set RESET wait timer
955
956 nstatus.treq_tbit := PSW.tflag; -- copy PSW.tflag to treq_bit
957 if PSW.tflag = '0' then -- if PSW tbit clear consider prefetch
958 -- The prefetch decision path can be critical (and was on s3). It uses
959 -- R_STATUS.intpend instead of int_pending, using the status latched
960 -- at the previous state is OK. It uses R_STATUS.treq_mmu because
961 -- no MMU trap can occur during this state (only in *_w states).
962 -- It does not check treq_ysv because pipelined instructions can't
963 -- trigger ysv traps, in contrast to MMU traps.
964 if ID_STAT.do_pref_dec='1' and -- prefetch possible
965 R_STATUS.intpend='0' and -- no interrupts
966 R_STATUS.treq_mmu='0' and -- no MMU trap request
967 R_STATUS.cpugo='1' and -- CPU on go
968 R_STATUS.cpususp='0' and -- CPU not suspended
969 not R_STATUS.cmdbusy='1' -- and no command pending
970 then -- then go for prefetch
971 nvmcntl.req := '1';
972 ndpcntl.gr_pcinc := '1'; -- (pc)++
973 nmmumoni.istart := '1';
974 nstatus.prefdone := '1';
975 end if;
976 end if;
977
978 if ID_STAT.do_fork_op = '1' then
979 case ID_STAT.fork_op is
980 when c_fork_op_halt => nstate := s_op_halt;
981 when c_fork_op_wait => nstate := s_op_wait;
982 when c_fork_op_rtti => nstate := s_rti_getpc;
983 when c_fork_op_trap => nstate := s_op_trap;
984 when c_fork_op_reset=> nstate := s_op_reset;
985 when c_fork_op_rts => nstate := s_op_rts;
986 when c_fork_op_spl => nstate := s_op_spl;
987 when c_fork_op_mcc => nstate := s_op_mcc;
988 when c_fork_op_br => nstate := s_op_br;
989 when c_fork_op_mark => nstate := s_op_mark;
990 when c_fork_op_sob => nstate := s_op_sob;
991 when c_fork_op_mtp => nstate := s_opa_mtp;
992 when others => nstate := s_cpufail;
993 end case;
994 elsif ID_STAT.do_fork_srcr = '1' then
995 case ID_STAT.fork_srcr is
996 when c_fork_srcr_def => nstate := s_srcr_def;
997 when c_fork_srcr_inc => nstate := s_srcr_inc;
998 when c_fork_srcr_dec => nstate := s_srcr_dec;
999 when c_fork_srcr_ind => nstate := s_srcr_ind;
1000 when others => nstate := s_cpufail;
1001 end case;
1002 elsif ID_STAT.do_fork_dstr = '1' then
1003 do_fork_dstr(nstate, ID_STAT);
1004 elsif ID_STAT.do_fork_dsta = '1' then
1005 case ID_STAT.fork_dsta is -- 2nd dsta fork in s_opa_mtp_pop_w
1006 when c_fork_dsta_def => do_fork_opa(nstate, ID_STAT);
1007 when c_fork_dsta_inc => nstate := s_dsta_inc;
1008 when c_fork_dsta_dec => nstate := s_dsta_dec;
1009 when c_fork_dsta_ind => nstate := s_dsta_ind;
1010 when others => nstate := s_cpufail;
1011 end case;
1012 elsif ID_STAT.do_fork_opg = '1' then
1013 do_fork_opg(nstate, ID_STAT);
1014 elsif ID_STAT.is_res = '1' then
1015 nstate := s_abort_10; -- do vector 10 abort;
1016 else
1017 nstate := s_cpufail; -- catch mistakes here...
1018 end if;
1019
1020 -- source read states -------------------------------------------------------
1021 -- flows:
1022 -- 1 (r) s_srcr_def req (r)
1023 -- s_srcr_def_w get (r)
1024 -- -> do_fork_dstr or do_fork_opg
1025 --
1026 -- 2 (r)+ s_srcr_inc req (r); r+=s
1027 -- s_srcr_inc_w get (r)
1028 -- -> do_fork_dstr or do_fork_opg
1029 --
1030 -- 3 @(r)+ s_srcr_inc req (r); r+=s
1031 -- s_srcr_inc_w get (r)
1032 -- s_srcr_def req @(r)
1033 -- s_srcr_def_w get @(r)
1034 -- -> do_fork_dstr or do_fork_opg
1035 --
1036 -- 4 -(r) s_srcr_dec r-=s
1037 -- s_srcr_dec1 req (r)
1038 -- s_srcr_inc_w get (r)
1039 -- -> do_fork_dstr or do_fork_opg
1040 --
1041 -- 5 @-(r) s_srcr_dec r-=s
1042 -- s_srcr_dec1 req (r)
1043 -- s_srcr_inc_w get (r)
1044 -- s_srcr_def req @(r)
1045 -- s_srcr_def_w get @(r)
1046 -- -> do_fork_dstr or do_fork_opg
1047 --
1048 -- 6 n(r) s_srcr_ind req n
1049 -- s_srcr_ind1_w get n; ea=r+n
1050 -- s_srcr_ind2 req n(r)
1051 -- s_srcr_ind2_w get n(r)
1052 -- -> do_fork_dstr or do_fork_opg
1053 --
1054 -- 7 @n(r) s_srcr_ind req n
1055 -- s_srcr_ind1_w get n; ea=r+n
1056 -- s_srcr_ind2 req n(r)
1057 -- s_srcr_ind2_w get n(r)
1058 -- s_srcr_def req @n(r)
1059 -- s_srcr_def_w get @n(r)
1060 -- -> do_fork_dstr or do_fork_opg
1061
1062 when s_srcr_def => -- -----------------------------------
1063 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
1064 do_memread_d(nstate, nvmcntl, s_srcr_def_w,
1065 pbytop=>R_IDSTAT.is_bytop,
1066 pispace=>R_IDSTAT.is_srcpcmode1);
1067
1068 when s_srcr_def_w => -- -----------------------------------
1069 nstate := s_srcr_def_w;
1070 do_memcheck(nstate, nstatus, imemok);
1071 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1072 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1073 if imemok then
1074 ndpcntl.dsrc_we := '1'; -- update DSRC
1075 if R_IDSTAT.do_fork_dstr = '1' then
1076 do_fork_dstr(nstate, R_IDSTAT);
1077 else
1078 do_fork_opg(nstate, R_IDSTAT);
1079 end if;
1080 end if;
1081
1082 when s_srcr_inc => -- -----------------------------------
1083 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
1084 do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
1085 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
1086 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1087 ndpcntl.gr_adst := SRCREG;
1088 ndpcntl.gr_we := '1';
1089 nmmumoni.regmod := '1';
1090 nmmumoni.isdec := '0';
1091 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
1092 if DSTREG = SRCREG then -- prevent stale DDST copy
1093 ndpcntl.ddst_we := '1'; -- update DDST
1094 end if;
1095 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
1096 bytop := R_IDSTAT.is_bytop and not SRCDEF;
1097 do_memread_d(nstate, nvmcntl, s_srcr_inc_w,
1098 pbytop=>bytop, pispace=>R_IDSTAT.is_srcpc);
1099
1100 when s_srcr_inc_w => -- -----------------------------------
1101 nstate := s_srcr_inc_w;
1102 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1103 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1104 do_memcheck(nstate, nstatus, imemok);
1105 if imemok then
1106 ndpcntl.dsrc_we := '1'; -- update DSRC
1107 if SRCDEF = '1' then
1108 nstate := s_srcr_def;
1109 else
1110 if R_IDSTAT.do_fork_dstr = '1' then
1111 do_fork_dstr(nstate, R_IDSTAT);
1112 else
1113 do_fork_opg(nstate, R_IDSTAT);
1114 end if;
1115 end if;
1116 end if;
1117
1118 when s_srcr_dec => -- -----------------------------------
1119 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
1120 do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
1121 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
1122 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
1123 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1124 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1125 ndpcntl.dsrc_we := '1'; -- update DSRC
1126 ndpcntl.gr_adst := SRCREG;
1127 ndpcntl.gr_we := '1';
1128 nmmumoni.regmod := '1';
1129 nmmumoni.isdec := '1';
1130 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
1131 if DSTREG = SRCREG then -- prevent stale DDST copy
1132 ndpcntl.ddst_we := '1'; -- update DDST
1133 end if;
1134 nstate := s_srcr_dec1;
1135
1136 when s_srcr_dec1 => -- -----------------------------------
1137 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
1138 bytop := R_IDSTAT.is_bytop and not SRCDEF;
1139 do_memread_d(nstate, nvmcntl, s_srcr_inc_w, pbytop=>bytop);
1140
1141 when s_srcr_ind => -- -----------------------------------
1142 do_memread_i(nstate, ndpcntl, nvmcntl, s_srcr_ind1_w);
1143
1144 when s_srcr_ind1_w => -- -----------------------------------
1145 nstate := s_srcr_ind1_w;
1146 if R_IDSTAT.is_srcpc = '0' then
1147 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A = DSRC
1148 else
1149 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
1150 end if;
1151 ndpcntl.ounit_bsel := c_ounit_bsel_vmdout; -- OUNIT B = VMDOUT
1152 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1153 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1154 ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
1155 do_memcheck(nstate, nstatus, imemok);
1156 if imemok then
1157 ndpcntl.dsrc_we := '1'; -- update DSRC
1158 ndpcntl.ddst_we := '1'; -- update DDST (to reload PC)
1159 nstate := s_srcr_ind2;
1160 end if;
1161
1162 when s_srcr_ind2 => -- -----------------------------------
1163 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
1164 bytop := R_IDSTAT.is_bytop and not SRCDEF;
1165 do_memread_d(nstate, nvmcntl, s_srcr_ind2_w, pbytop=>bytop);
1166
1167 when s_srcr_ind2_w => -- -----------------------------------
1168 nstate := s_srcr_ind2_w;
1169 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1170 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1171 do_memcheck(nstate, nstatus, imemok);
1172 if imemok then
1173 ndpcntl.dsrc_we := '1'; -- update DSRC
1174 if SRCDEF = '1' then
1175 nstate := s_srcr_def;
1176 else
1177 if R_IDSTAT.do_fork_dstr = '1' then
1178 do_fork_dstr(nstate, R_IDSTAT);
1179 else
1180 do_fork_opg(nstate, R_IDSTAT);
1181 end if;
1182 end if;
1183 end if;
1184
1185 -- destination read states --------------------------------------------------
1186 -- flows:
1187 -- 1 (r) s_dstr_def req (r) (rmw if rmw op)
1188 -- s_dstr_def_w get (r)
1189 -- -> do_fork_opg
1190 --
1191 -- 2 (r)+ s_dstr_inc req (r); r+=s (rmw if rmw op)
1192 -- s_dstr_inc_w get (r)
1193 -- -> do_fork_opg
1194 --
1195 -- 3 @(r)+ s_dstr_inc req (r); r+=s
1196 -- s_dstr_inc_w get (r)
1197 -- s_dstr_def req @(r) (rmw if rmw op)
1198 -- s_dstr_def_w get @(r)
1199 -- -> do_fork_opg
1200 --
1201 -- 4 -(r) s_dstr_dec r-=s
1202 -- s_dstr_dec1 req (r) (rmw if rmw op)
1203 -- s_dstr_inc_w get (r)
1204 -- -> do_fork_opg
1205 --
1206 -- 5 @-(r) s_dstr_dec r-=s
1207 -- s_dstr_dec1 req (r)
1208 -- s_dstr_inc_w get (r)
1209 -- s_dstr_def req @(r) (rmw if rmw op)
1210 -- s_dstr_def_w get @(r)
1211 -- -> do_fork_opg
1212 --
1213 -- 6 n(r) s_dstr_ind req n
1214 -- s_dstr_ind1_w get n; ea=r+n
1215 -- s_dstr_ind2 req n(r) (rmw if rmw op)
1216 -- s_dstr_ind2_w get n(r)
1217 -- -> do_fork_opg
1218 --
1219 -- 7 @n(r) s_dstr_ind req n
1220 -- s_dstr_ind1_w get n; ea=r+n
1221 -- s_dstr_ind2 req n(r)
1222 -- s_dstr_ind2_w get n(r)
1223 -- s_dstr_def req @n(r) (rmw if rmw op)
1224 -- s_dstr_def_w get @n(r)
1225 -- -> do_fork_opg
1226
1227 when s_dstr_def => -- -----------------------------------
1228 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1229 do_memread_d(nstate, nvmcntl, s_dstr_def_w,
1230 pbytop=>R_IDSTAT.is_bytop, pmacc=>R_IDSTAT.is_rmwop,
1231 pispace=>R_IDSTAT.is_dstpcmode1,
1232 pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
1233
1234 when s_dstr_def_w => -- -----------------------------------
1235 nstate := s_dstr_def_w;
1236 do_memcheck(nstate, nstatus, imemok);
1237 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1238 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1239 if imemok then
1240 ndpcntl.ddst_we := '1'; -- update DDST
1241 do_fork_opg(nstate, R_IDSTAT);
1242 end if;
1243
1244 when s_dstr_inc => -- -----------------------------------
1245 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
1246 do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
1247 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
1248 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1249 ndpcntl.gr_adst := DSTREG;
1250 ndpcntl.gr_we := '1';
1251 nmmumoni.regmod := '1';
1252 nmmumoni.isdec := '0';
1253 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1254 macc := R_IDSTAT.is_rmwop and not DSTDEF;
1255 bytop := R_IDSTAT.is_bytop and not DSTDEF;
1256 do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
1257 pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc,
1258 pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
1259
1260 when s_dstr_inc_w => -- -----------------------------------
1261 nstate := s_dstr_inc_w;
1262 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1263 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1264 do_memcheck(nstate, nstatus, imemok);
1265 if imemok then
1266 ndpcntl.ddst_we := '1'; -- update DDST
1267 if DSTDEF = '1' then
1268 nstate := s_dstr_def;
1269 else
1270 do_fork_opg(nstate, R_IDSTAT);
1271 end if;
1272 end if;
1273
1274 when s_dstr_dec => -- -----------------------------------
1275 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
1276 do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
1277 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
1278 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
1279 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1280 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1281 ndpcntl.ddst_we := '1'; -- update DDST
1282 ndpcntl.gr_adst := DSTREG;
1283 ndpcntl.gr_we := '1';
1284 nmmumoni.regmod := '1';
1285 nmmumoni.isdec := '1';
1286 nstate := s_dstr_dec1;
1287
1288 when s_dstr_dec1 => -- -----------------------------------
1289 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1290 macc := R_IDSTAT.is_rmwop and not DSTDEF;
1291 bytop := R_IDSTAT.is_bytop and not DSTDEF;
1292 do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
1293 pbytop=>bytop, pmacc=>macc,
1294 pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
1295
1296 when s_dstr_ind => -- -----------------------------------
1297 do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
1298
1299 when s_dstr_ind1_w => -- -----------------------------------
1300 nstate := s_dstr_ind1_w;
1301 if R_IDSTAT.is_dstpc = '0' then
1302 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
1303 else
1304 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
1305 end if;
1306 ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
1307 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1308 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1309 do_memcheck(nstate, nstatus, imemok);
1310 if imemok then
1311 ndpcntl.ddst_we := '1'; -- update DDST
1312 nstate := s_dstr_ind2;
1313 end if;
1314
1315 when s_dstr_ind2 => -- -----------------------------------
1316 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1317 macc := R_IDSTAT.is_rmwop and not DSTDEF;
1318 bytop := R_IDSTAT.is_bytop and not DSTDEF;
1319 do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
1320 pbytop=>bytop, pmacc=>macc,
1321 pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
1322
1323 when s_dstr_ind2_w => -- -----------------------------------
1324 nstate := s_dstr_ind2_w;
1325 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1326 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1327 do_memcheck(nstate, nstatus, imemok);
1328 if imemok then
1329 ndpcntl.ddst_we := '1'; -- update DDST
1330 if DSTDEF = '1' then
1331 nstate := s_dstr_def;
1332 else
1333 do_fork_opg(nstate, R_IDSTAT);
1334 end if;
1335 end if;
1336
1337 -- destination write states -------------------------------------------------
1338 -- flows:
1339 -- 1 (r) s_dstw_def wreq (r) check kstack
1340 -- s_dstw_def_w ack (r)
1341 -- -> do_fork_next
1342 --
1343 -- 2 (r)+ s_dstw_inc wreq (r) check kstack
1344 -- s_dstw_inc_w ack (r); r+=s
1345 -- -> do_fork_next
1346 --
1347 -- 3 @(r)+ s_dstw_inc rreq (r); r+=s
1348 -- s_dstw_incdef_w get (r)
1349 -- s_dstw_def246 wreq @(r)
1350 -- s_dstw_def_w ack @(r)
1351 -- -> do_fork_next
1352 --
1353 -- 4 -(r) s_dstw_dec r-=s
1354 -- s_dstw_dec1 wreq (r) check kstack
1355 -- s_dstw_def_w ack (r)
1356 -- -> do_fork_next
1357 --
1358 -- 5 @-(r) s_dstw_dec r-=s
1359 -- s_dstw_dec1 rreq (r)
1360 -- s_dstw_incdef_w get (r)
1361 -- s_dstw_def246 wreq @(r)
1362 -- s_dstw_def_w ack @(r)
1363 -- -> do_fork_next
1364 --
1365 -- 6 n(r) s_dstw_ind rreq n
1366 -- s_dstw_ind_w get n; ea=r+n
1367 -- s_dstw_dec1 wreq n(r) check kstack
1368 -- s_dstw_def_w ack n(r)
1369 -- -> do_fork_next
1370 --
1371 -- 7 @n(r) s_dstw_ind rreq n
1372 -- s_dstw_ind_w get n; ea=r+n
1373 -- s_dstw_dec1 rreq n(r)
1374 -- s_dstw_incdef_w get n(r)
1375 -- s_dstw_def246 wreq @n(r)
1376 -- s_dstw_def_w ack @n(r)
1377 -- -> do_fork_next
1378
1379 when s_dstw_def => -- -----------------------------------
1380 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1381 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1382 nvmcntl.kstack := is_kstackdst1246;
1383 do_memwrite(nstate, nvmcntl, s_dstw_def_w, pispace=>R_IDSTAT.is_dstpc);
1384
1385 when s_dstw_def_w => -- -----------------------------------
1386 nstate := s_dstw_def_w;
1387 do_memcheck(nstate, nstatus, imemok);
1388 if imemok then
1389 ndpcntl.psr_ccwe := '1';
1390 idm_idone := '1'; -- instruction done
1391 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1392 end if;
1393
1394 when s_dstw_inc => -- -----------------------------------
1395 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1396 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for else)
1397 do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG); --(...)
1398 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
1399 if DSTDEF = '0' then
1400 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1401 nvmcntl.kstack := is_kstackdst1246;
1402 do_memwrite(nstate, nvmcntl, s_dstw_inc_w, pispace=>R_IDSTAT.is_dstpc);
1403 nstatus.do_grwe := '1';
1404 else
1405 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1406 ndpcntl.gr_adst := DSTREG;
1407 ndpcntl.gr_we := '1';
1408 nmmumoni.regmod := '1';
1409 nmmumoni.isdec := '0';
1410 do_memread_d(nstate, nvmcntl, s_dstw_incdef_w,
1411 pispace=>R_IDSTAT.is_dstpc);
1412 end if;
1413
1414 when s_dstw_inc_w => -- -----------------------------------
1415 nstate := s_dstw_inc_w;
1416 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
1417 do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
1418 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
1419 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1420 ndpcntl.gr_adst := DSTREG;
1421 if R_STATUS.do_grwe = '1' then
1422 nmmumoni.regmod := '1';
1423 nmmumoni.isdec := '0';
1424 nmmumoni.trace_prev := '1'; -- mmr freeze of prev state
1425 ndpcntl.gr_we := '1'; -- update DST reg
1426 end if;
1427 nstatus.do_grwe := '0';
1428 do_memcheck(nstate, nstatus, imemok);
1429 if imemok then
1430 ndpcntl.psr_ccwe := '1';
1431 idm_idone := '1'; -- instruction done
1432 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1433 end if;
1434
1435 when s_dstw_incdef_w => -- -----------------------------------
1436 nstate := s_dstw_incdef_w;
1437 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1438 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1439 do_memcheck(nstate, nstatus, imemok);
1440 if imemok then
1441 ndpcntl.ddst_we := '1'; -- update DDST
1442 nstate := s_dstw_def246;
1443 end if;
1444
1445 when s_dstw_dec => -- -----------------------------------
1446 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
1447 do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
1448 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
1449 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
1450 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1451 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1452 ndpcntl.ddst_we := '1'; -- update DDST
1453 ndpcntl.gr_adst := DSTREG;
1454 ndpcntl.gr_we := '1';
1455 nmmumoni.regmod := '1';
1456 nmmumoni.isdec := '1';
1457 nstate := s_dstw_dec1;
1458
1459 when s_dstw_dec1 => -- -----------------------------------
1460 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1461 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if)
1462 if DSTDEF = '0' then
1463 nvmcntl.kstack := is_kstackdst1246;
1464 do_memwrite(nstate, nvmcntl, s_dstw_def_w);
1465 else
1466 do_memread_d(nstate, nvmcntl, s_dstw_incdef_w);
1467 end if;
1468
1469 when s_dstw_ind => -- -----------------------------------
1470 do_memread_i(nstate, ndpcntl, nvmcntl, s_dstw_ind_w);
1471
1472 when s_dstw_ind_w => -- -----------------------------------
1473 nstate := s_dstw_ind_w;
1474 if R_IDSTAT.is_dstpc = '0' then
1475 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
1476 else
1477 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
1478 end if;
1479 ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
1480 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1481 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1482 do_memcheck(nstate, nstatus, imemok);
1483 if imemok then
1484 ndpcntl.ddst_we := '1'; -- update DDST
1485 nstate := s_dstw_dec1;
1486 end if;
1487
1488 when s_dstw_def246 => -- -----------------------------------
1489 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1490 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1491 do_memwrite(nstate, nvmcntl, s_dstw_def_w);
1492
1493 -- destination address states -----------------------------------------------
1494 -- flows:
1495 -- 1 (r) -> do_fork_opa
1496 --
1497 -- 2 (r)+ s_dsta_inc r+=2
1498 -- -> do_fork_opa
1499 --
1500 -- 3 @(r)+ s_dsta_inc req (r); r+=s
1501 -- s_dsta_incdef_w get (r)
1502 -- -> do_fork_opa
1503 --
1504 -- 4 -(r) s_dsta_dec r-=s
1505 -- s_dsta_dec1 ?? FIXME ?? what is done here ??
1506 -- -> do_fork_opa
1507 --
1508 -- 5 @-(r) s_dsta_dec r-=s
1509 -- s_dsta_dec1 req (r)
1510 -- s_dsta_incdef_w get (r)
1511 -- -> do_fork_opa
1512 --
1513 -- 6 n(r) s_dsta_ind req n
1514 -- s_dsta_ind_w get n; ea=r+n
1515 -- s_dsta_dec1 ?? FIXME ?? what is done here ??
1516 -- -> do_fork_opa
1517 --
1518 -- 7 @n(r) s_dsta_ind req n
1519 -- s_dsta_ind_w get n; ea=r+n
1520 -- s_dsta_dec1 req n(r)
1521 -- s_dsta_incdef_w get n(r)
1522 -- -> do_fork_opa
1523
1524 when s_dsta_inc => -- -----------------------------------
1525 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
1526 ndpcntl.ounit_const := "000000010";
1527 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
1528 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1529 ndpcntl.gr_adst := DSTREG;
1530 ndpcntl.gr_we := '1';
1531 nmmumoni.regmod := '1';
1532 nmmumoni.isdec := '0';
1533 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
1534 if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
1535 ndpcntl.dsrc_we := '1'; -- update DSRC
1536 end if;
1537 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1538 if DSTDEF = '0' then
1539 do_fork_opa(nstate, R_IDSTAT);
1540 else
1541 do_memread_d(nstate, nvmcntl, s_dsta_incdef_w,
1542 pispace=>R_IDSTAT.is_dstpc);
1543 end if;
1544
1545 when s_dsta_incdef_w => -- -----------------------------------
1546 nstate := s_dsta_incdef_w;
1547 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1548 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1549 do_memcheck(nstate, nstatus, imemok);
1550 if imemok then
1551 ndpcntl.ddst_we := '1'; -- update DDST
1552 do_fork_opa(nstate, R_IDSTAT);
1553 end if;
1554
1555 when s_dsta_dec => -- -----------------------------------
1556 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
1557 ndpcntl.ounit_const := "000000010";
1558 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(2)
1559 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
1560 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1561 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1562 ndpcntl.ddst_we := '1'; -- update DDST
1563 ndpcntl.gr_adst := DSTREG;
1564 ndpcntl.gr_we := '1';
1565 nmmumoni.regmod := '1';
1566 nmmumoni.isdec := '1';
1567 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
1568 if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
1569 ndpcntl.dsrc_we := '1'; -- update DSRC
1570 end if;
1571 nstate := s_dsta_dec1;
1572
1573 when s_dsta_dec1 => -- -----------------------------------
1574 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
1575 if DSTDEF = '0' then -- check here used also by
1576 do_fork_opa(nstate, R_IDSTAT); -- s_dsta_ind flow !!
1577 else
1578 do_memread_d(nstate, nvmcntl, s_dsta_incdef_w);
1579 end if;
1580
1581 when s_dsta_ind => -- -----------------------------------
1582 do_memread_i(nstate, ndpcntl, nvmcntl, s_dsta_ind_w);
1583
1584 when s_dsta_ind_w => -- -----------------------------------
1585 nstate := s_dsta_ind_w;
1586 if R_IDSTAT.is_dstpc = '0' then
1587 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
1588 else
1589 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
1590 end if;
1591 ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
1592 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1593 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
1594 do_memcheck(nstate, nstatus, imemok);
1595 if imemok then
1596 ndpcntl.ddst_we := '1'; -- update DDST
1597 nstate := s_dsta_dec1;
1598 end if;
1599
1600 -- instruction operate states -----------------------------------------------
1601
1602 when s_op_halt => -- HALT -------------------------------
1603 idm_idone := '1'; -- instruction done
1604 if is_kmode = '1' then -- if in kernel mode execute
1605 nstatus.cpugo := '0';
1606 nstatus.cpurust := c_cpurust_halt;
1607 nstate := s_idle;
1608 else -- otherwise trap
1609 ncpuerr.illhlt := '1';
1610 nstate := s_abort_4; -- vector 4 abort like 11/70
1611 end if;
1612
1613 when s_op_wait => -- WAIT ------------------------------
1614 -- Note: wait is the only interruptable instruction. The CPU spins
1615 -- in s_op_wait until an interrupt or a control command is seen.
1616 -- In case of a control command R_STATUS.waitsusp is set and
1617 -- control transfered to s_idle. If the control command returns
1618 -- to s_op_wait, waitsusp is cleared here. This ensures that the
1619 -- idm_idone logic (for dmcmon) sees only one WAIT even if it is
1620 -- interrupted by control commands.
1621 ndpcntl.gr_asrc := "000"; -- load R0 in DSRC for DR emulation
1622 ndpcntl.dsrc_sel := c_dpath_dsrc_src;
1623 ndpcntl.dsrc_we := '1';
1624 nstatus.waitsusp := '0'; -- in case of returning from s_idle
1625
1626 -- signal idone in the first cycle of a WAIT instruction to dmcmon
1627 -- ensures that a WAIT is logged once and only once
1628 idm_idone := not (R_STATUS.waitsusp or R_STATUS.cpuwait);
1629
1630 nstate := s_op_wait; -- spin here
1631 if is_kmode = '0' then -- but act as nop if not in kernel
1632 nstate := s_idle;
1633 elsif int_pending = '1' or -- bail out if pending interrupt
1634 R_STATUS.cpustep='1' then -- or the instruction is only stepped
1635 nstate := s_idle;
1636 elsif R_STATUS.cmdbusy = '1' then -- suspend if a cp command is pending
1637 nstatus.waitsusp := '1';
1638 nstate := s_idle;
1639 else
1640 nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait
1641 nstatus.itimer := '1'; -- itimer will stay 1 during a WAIT
1642 end if;
1643
1644 when s_op_trap => -- trap instructions (IOT,BPT,..) ----
1645 idm_idone := '1'; -- instruction done
1646 lvector := "0000" & R_IDSTAT.trap_vec; -- vector
1647 do_start_vec(nstate, ndpcntl, lvector);
1648
1649 when s_op_reset => -- RESET -----------------------------
1650 nstate := s_op_reset; -- default is spin till timer expire
1651 nstatus.resetcnt := slv(unsigned(R_STATUS.resetcnt) - 1); -- dec timer
1652 if is_kmode = '1' then -- if in kernel mode execute
1653 if R_STATUS.resetcnt = "111" then -- in first cycle
1654 nstatus.breset := '1'; -- issue bus reset
1655 end if;
1656 if R_STATUS.resetcnt = "000" then -- in last cycle
1657 nstate := s_idle; -- done, continue via s_idle
1658 end if;
1659 else -- if not in kernel mode
1660 nstate := s_idle; -- nop, continue via s_idle
1661 end if;
1662
1663 when s_op_rts => -- RTS -------------------------------
1664 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
1665 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
1666 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1667 ndpcntl.gr_adst := c_gr_pc;
1668 ndpcntl.gr_we := '1'; -- load PC with reg(dst)
1669 idm_pcload := '1'; -- signal flow change
1670 nstate := s_op_rts_pop;
1671
1672 when s_op_rts_pop => -- -----------------------------------
1673 do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_rts_pop_w,
1674 nmmumoni, pupdt_sp=>'1');
1675
1676 when s_op_rts_pop_w => -- -----------------------------------
1677 nstate := s_op_rts_pop_w;
1678 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1679 ndpcntl.gr_adst := DSTREG;
1680 do_memcheck(nstate, nstatus, imemok);
1681 if imemok then
1682 ndpcntl.gr_we := '1'; -- load R with (SP)+
1683 idm_idone := '1'; -- instruction done
1684 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1685 end if;
1686
1687 when s_op_spl => -- SPL -------------------------------
1688 ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
1689 ndpcntl.psr_func := c_psr_func_wspl;
1690 idm_idone := '1'; -- instruction done
1691 if is_kmode = '1' then -- active only in kernel mode
1692 ndpcntl.psr_we := '1';
1693 nstate := s_ifetch; -- unconditionally fetch next
1694 -- instruction like a 11/70
1695 -- no interrupt recognition !
1696 else
1697 do_fork_next(nstate, nstatus, nmmumoni); -- in non-kernel, noop
1698 end if;
1699
1700 when s_op_mcc => -- CLx/SEx ---------------------------
1701 ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
1702 ndpcntl.psr_func := c_psr_func_wcc;
1703 ndpcntl.psr_we := '1';
1704 idm_idone := '1'; -- instruction done
1705 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1706
1707 when s_op_br => -- BR --------------------------------
1708 nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
1709 ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
1710 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
1711 ndpcntl.ounit_bsel := c_ounit_bsel_ireg8;-- OUNIT B = IREG8
1712 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1713 -- note: cc are NZVC
1714 case brcode(3 downto 1) is
1715 when "000" => -- BR
1716 brcond := '1';
1717 when "001" => -- BNE/BEQ: if Z = x
1718 brcond := PSW.cc(2);
1719 when "010" => -- BGE/BLT: if N xor V = x
1720 brcond := PSW.cc(3) xor PSW.cc(1);
1721 when "011" => -- BGT/BLE: if Z or (N xor V) = x
1722 brcond := PSW.cc(2) or (PSW.cc(3) xor PSW.cc(1));
1723 when "100" => -- BPL/BMI: if N = x
1724 brcond := PSW.cc(3);
1725 when "101" => -- BHI/BLOS:if C or Z = x
1726 brcond := PSW.cc(2) or PSW.cc(0);
1727 when "110" => -- BVC/BVS: if V = x
1728 brcond := PSW.cc(1);
1729 when "111" => -- BCC/BCS: if C = x
1730 brcond := PSW.cc(0);
1731 when others => null;
1732 end case;
1733
1734 ndpcntl.gr_adst := c_gr_pc;
1735 idm_idone := '1'; -- instruction done
1736 if brcond = brcode(0) then -- this coding creates redundant code
1737 ndpcntl.gr_we := '1'; -- but synthesis optimizes this way !
1738 idm_pcload := '1'; -- signal flow change
1739 do_fork_next(nstate, nstatus, nmmumoni);
1740 else
1741 do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
1742 end if;
1743
1744 when s_op_mark => -- MARK ------------------------------
1745 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
1746 ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
1747 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1748 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1749 ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
1750 ndpcntl.gr_adst := c_gr_r5; -- fetch r5
1751 ndpcntl.ddst_sel := c_dpath_ddst_dst;
1752 ndpcntl.ddst_we := '1';
1753 nstate := s_op_mark1;
1754
1755 when s_op_mark1 => -- -----------------------------------
1756 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
1757 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
1758 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1759 ndpcntl.gr_adst := c_gr_pc;
1760 ndpcntl.gr_we := '1'; -- load PC with r5
1761 idm_pcload := '1'; -- signal flow change
1762 nstate := s_op_mark_pop;
1763
1764 when s_op_mark_pop => -- -----------------------------------
1765 do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_mark_pop_w,
1766 nmmumoni, pupdt_sp=>'1');
1767
1768 when s_op_mark_pop_w => -- -----------------------------------
1769 nstate := s_op_mark_pop_w;
1770 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
1771 ndpcntl.gr_adst := c_gr_r5;
1772 do_memcheck(nstate, nstatus, imemok);
1773 if imemok then
1774 ndpcntl.gr_we := '1'; -- load R5 with (sp)+
1775 idm_idone := '1'; -- instruction done
1776 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1777 end if;
1778
1779 when s_op_sob => -- SOB (dec) -------------------------
1780 -- comment fork_next_pref out (blog 2006-10-02) due to synthesis impact
1781 --nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
1782 --ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
1783 ndpcntl.dres_sel := R_IDSTAT.res_sel;
1784 ndpcntl.gr_adst := SRCREG;
1785 ndpcntl.gr_we := '1';
1786
1787 if DP_STAT.ccout_z = '0' then -- if z=0 branch, if z=1 fall thru
1788 nstate := s_op_sob1;
1789 else
1790 --do_fork_next_pref(nstate, ndpcntl, nvmcntl, nmmumoni);
1791 idm_idone := '1'; -- instruction done
1792 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1793 end if;
1794
1795 when s_op_sob1 => -- SOB (br) --------------------------
1796 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
1797 ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
1798 ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
1799 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1800 ndpcntl.gr_adst := c_gr_pc;
1801 ndpcntl.gr_we := '1';
1802 idm_pcload := '1'; -- signal flow change
1803 idm_idone := '1'; -- instruction done
1804 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1805
1806 when s_opg_gen => -- -----------------------------------
1807 nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
1808 ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
1809 ndpcntl.gr_bytop := R_IDSTAT.is_bytop;
1810 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1811
1812 if R_IDSTAT.op_mov = '1' then -- in case of MOV xx,R
1813 ndpcntl.gr_bytop := '0'; -- no bytop, do sign extend
1814 end if;
1815
1816 ndpcntl.psr_ccwe := '1'; -- acceptable even here though before the final
1817 -- write which is a macc completion. That can
1818 -- only fail due to a ibus timeout, all other
1819 -- errors were caught during initial read.
1820
1821 if R_IDSTAT.is_dstw_reg = '1' then
1822 ndpcntl.gr_we := '1';
1823 end if;
1824
1825 if R_IDSTAT.is_rmwop = '1' then
1826 do_memwrite(nstate, nvmcntl, s_opg_gen_rmw_w, pmacc=>'1');
1827 else
1828 idm_idone := '1'; -- instruction done
1829 if R_STATUS.prefdone = '1' then
1830 nstatus.prefdone :='0';
1831 nstate := s_ifetch_w;
1832 do_memcheck(nstate, nstatus, imemok);
1833 if imemok then
1834 ndpcntl.ireg_we := '1';
1835 nstate := s_idecode;
1836 end if;
1837 else
1838 if R_IDSTAT.is_dstw_pc = '1' then
1839 nstate := s_idle;
1840 else
1841 do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
1842 end if;
1843 end if;
1844 end if;
1845
1846 when s_opg_gen_rmw_w => -- -----------------------------------
1847 nstate := s_opg_gen_rmw_w;
1848 do_memcheck(nstate, nstatus, imemok);
1849 if imemok then
1850 idm_idone := '1'; -- instruction done
1851 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1852 end if;
1853
1854 when s_opg_mul => -- MUL (oper) ------------------------
1855 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1856 ndpcntl.gr_adst := SRCREG; -- write high order result
1857 ndpcntl.gr_we := '1';
1858 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1859 ndpcntl.dsrc_we := '1'; -- capture high order part
1860 ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
1861 ndpcntl.dtmp_we := '1'; -- capture low order part
1862 nstate := s_opg_mul1;
1863
1864 when s_opg_mul1 => -- MUL (write odd reg) ---------------
1865 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
1866 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
1867 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1868 ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
1869 ndpcntl.gr_we := '1';
1870 ndpcntl.psr_ccwe := '1';
1871 idm_idone := '1'; -- instruction done
1872 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1873
1874 when s_opg_div => -- DIV (load dd_low) -----------------
1875 ndpcntl.munit_s_div := '1';
1876 ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
1877 ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
1878 ndpcntl.dtmp_we := '1';
1879 nstate := s_opg_div_cn;
1880
1881 when s_opg_div_cn => -- DIV (1st...16th cycle) ------------
1882 ndpcntl.munit_s_div_cn := '1';
1883 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1884 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1885 ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
1886 nstate := s_opg_div_cn;
1887 if DP_STAT.div_quit = '1' then
1888 nstate := s_opg_div_quit;
1889 else
1890 ndpcntl.dsrc_we := '1'; -- update DSRC
1891 ndpcntl.dtmp_we := '1'; -- update DTMP
1892 end if;
1893 if DP_STAT.shc_tc = '1' then
1894 nstate := s_opg_div_cr;
1895 end if;
1896
1897 when s_opg_div_cr => -- DIV (remainder correction) --------
1898 ndpcntl.munit_s_div_cr := '1';
1899 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1900 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1901 ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
1902 nstate := s_opg_div_sq;
1903
1904 when s_opg_div_sq => -- DIV (correct and store quotient) --
1905 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
1906 ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
1907 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
1908 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1909 ndpcntl.gr_adst := SRCREG; -- write result
1910 ndpcntl.gr_we := '1';
1911 ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
1912 ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
1913 nstate := s_opg_div_sr;
1914
1915 when s_opg_div_sr => -- DIV (store remainder) -------------
1916 ndpcntl.munit_s_div_sr := '1';
1917 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
1918 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
1919 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1920 ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
1921 ndpcntl.gr_we := '1';
1922 ndpcntl.psr_ccwe := '1';
1923 if DP_STAT.div_quit = '1' then
1924 nstate := s_opg_div_quit;
1925 else
1926 idm_idone := '1'; -- instruction done
1927 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1928 end if;
1929
1930 when s_opg_div_quit => -- DIV (0/ or /0 or V=1 aborts) ------
1931 ndpcntl.psr_ccwe := '1';
1932 idm_idone := '1'; -- instruction done
1933 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1934
1935 when s_opg_ash => -- ASH (load shc) --------------------
1936 ndpcntl.munit_s_ash := '1';
1937 nstate := s_opg_ash_cn;
1938
1939 when s_opg_ash_cn => -- ASH (shift cycles) ----------------
1940 nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
1941 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1942 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
1943 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
1944 ndpcntl.gr_adst := SRCREG; -- write result
1945 ndpcntl.munit_s_ash_cn := '1';
1946 ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
1947 nstate := s_opg_ash_cn;
1948 if DP_STAT.shc_tc = '0' then
1949 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1950 ndpcntl.dsrc_we := '1'; -- update DSRC
1951 else
1952 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1953 ndpcntl.gr_we := '1';
1954 ndpcntl.psr_ccwe := '1';
1955 idm_idone := '1'; -- instruction done
1956 do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
1957 end if;
1958
1959 when s_opg_ashc => -- ASHC (load low, load shc) ---------
1960 ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
1961 ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
1962 ndpcntl.dtmp_we := '1';
1963 ndpcntl.munit_s_ashc := '1';
1964 nstate := s_opg_ashc_cn;
1965
1966 when s_opg_ashc_cn => -- ASHC (shift cycles) ---------------
1967 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
1968 ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
1969 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
1970 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
1971 ndpcntl.gr_adst := SRCREG; -- write result
1972 ndpcntl.munit_s_ashc_cn := '1';
1973 nstate := s_opg_ashc_cn;
1974 if DP_STAT.shc_tc = '0' then
1975 ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1976 ndpcntl.dsrc_we := '1'; -- update DSRC
1977 ndpcntl.dtmp_we := '1'; -- update DTMP
1978 else
1979 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1980 ndpcntl.gr_we := '1';
1981 ndpcntl.psr_ccwe := '1';
1982 nstate := s_opg_ashc_wl;
1983 end if;
1984
1985 when s_opg_ashc_wl => -- ASHC (write low) ------------------
1986 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
1987 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
1988 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
1989 ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
1990 ndpcntl.gr_we := '1';
1991 idm_idone := '1'; -- instruction done
1992 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
1993
1994 -- dsta mode operations -----------------------------------------------------
1995
1996 when s_opa_jsr => -- -----------------------------------
1997 ndpcntl.gr_asrc := c_gr_sp; -- (for else)
1998 ndpcntl.dsrc_sel := c_dpath_dsrc_src; -- DSRC = regfile (for else)
1999 if R_IDSTAT.is_dstmode0 = '1' then
2000 nstate := s_abort_10; -- vector 10 abort like 11/70
2001 else
2002 ndpcntl.dsrc_we := '1';
2003 nstate := s_opa_jsr1;
2004 end if;
2005
2006 when s_opa_jsr1 => -- -----------------------------------
2007 ndpcntl.gr_asrc := SRCREG;
2008 ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
2009 ndpcntl.dtmp_we := '1';
2010
2011 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
2012 ndpcntl.ounit_const := "000000010";
2013 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
2014 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
2015 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2016 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
2017 ndpcntl.dsrc_we := '1'; -- update DDST
2018 ndpcntl.gr_adst := c_gr_sp;
2019 ndpcntl.gr_we := '1'; -- update SP
2020 nmmumoni.regmod := '1';
2021 nmmumoni.isdec := '1';
2022 nstate := s_opa_jsr_push;
2023
2024 when s_opa_jsr_push => -- -----------------------------------
2025 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
2026 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
2027 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2028 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
2029 nvmcntl.dspace := '1';
2030 nvmcntl.kstack := is_kmode;
2031 nvmcntl.wacc := '1';
2032 nvmcntl.req := '1';
2033 nstate := s_opa_jsr_push_w;
2034
2035 when s_opa_jsr_push_w => -- -----------------------------------
2036 nstate := s_opa_jsr_push_w;
2037 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
2038 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
2039 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2040 ndpcntl.gr_adst := SRCREG;
2041 do_memcheck(nstate, nstatus, imemok);
2042 if imemok then
2043 ndpcntl.gr_we := '1'; -- load R with PC
2044 nstate := s_opa_jsr2;
2045 end if;
2046
2047 when s_opa_jsr2 => -- -----------------------------------
2048 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
2049 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
2050 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2051 ndpcntl.gr_adst := c_gr_pc;
2052 ndpcntl.gr_we := '1'; -- load PC with dsta
2053 idm_pcload := '1'; -- signal flow change
2054 idm_idone := '1'; -- instruction done
2055 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
2056
2057 when s_opa_jmp => -- -----------------------------------
2058 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
2059 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
2060 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2061 ndpcntl.gr_adst := c_gr_pc;
2062 if R_IDSTAT.is_dstmode0 = '1' then
2063 nstate := s_abort_10; -- vector 10 abort like 11/70
2064 else
2065 ndpcntl.gr_we := '1'; -- load PC with dsta
2066 idm_pcload := '1'; -- signal flow change
2067 idm_idone := '1'; -- instruction done
2068 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
2069 end if;
2070
2071 when s_opa_mtp => -- -----------------------------------
2072 do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_opa_mtp_pop_w,
2073 nmmumoni, pupdt_sp=>'1');
2074
2075 when s_opa_mtp_pop_w => -- -----------------------------------
2076 nstate := s_opa_mtp_pop_w;
2077 ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
2078 ndpcntl.ddst_we := '1'; -- update DDST (needed for sp)
2079 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
2080 ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
2081 do_memcheck(nstate, nstatus, imemok);
2082 if imemok then
2083 ndpcntl.dtmp_we := '1'; -- load DTMP
2084 if R_IDSTAT.is_dstmode0 = '1' then -- handle register access
2085 nstate := s_opa_mtp_reg;
2086 else
2087 case R_IDSTAT.fork_dsta is -- 2nd dsta fork in s_idecode
2088 when c_fork_dsta_def => nstate := s_opa_mtp_mem;
2089 when c_fork_dsta_inc => nstate := s_dsta_inc;
2090 when c_fork_dsta_dec => nstate := s_dsta_dec;
2091 when c_fork_dsta_ind => nstate := s_dsta_ind;
2092 when others => nstate := s_cpufail;
2093 end case;
2094 end if;
2095 end if;
2096
2097 when s_opa_mtp_reg => -- -----------------------------------
2098 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
2099 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
2100 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2101 ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
2102 ndpcntl.gr_mode := PSW.pmode; -- load reg in pmode
2103 ndpcntl.gr_we := '1';
2104 idm_idone := '1'; -- instruction done
2105 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
2106
2107 when s_opa_mtp_mem => -- -----------------------------------
2108 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
2109 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
2110 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2111 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst;-- VA = DDST
2112 nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
2113 nvmcntl.mode := PSW.pmode;
2114 nvmcntl.wacc := '1';
2115 nvmcntl.req := '1';
2116 nstate := s_opa_mtp_mem_w;
2117
2118 when s_opa_mtp_mem_w => -- -----------------------------------
2119 nstate := s_opa_mtp_mem_w;
2120 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP (for cc)
2121 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0) (for cc)
2122 do_memcheck(nstate, nstatus, imemok);
2123 if imemok then
2124 ndpcntl.psr_ccwe := '1'; -- set cc (ounit via res_sel)
2125 idm_idone := '1'; -- instruction done
2126 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
2127 end if;
2128
2129 when s_opa_mfp_reg => -- -----------------------------------
2130 ndpcntl.gr_mode := PSW.pmode; -- fetch reg in pmode
2131 ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = reg(dst)
2132 ndpcntl.ddst_we := '1';
2133 nstate := s_opa_mfp_dec;
2134
2135 when s_opa_mfp_mem => -- -----------------------------------
2136 ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
2137 if PSW.cmode=c_psw_umode and -- if cm=pm=user then
2138 PSW.cmode=c_psw_umode then -- MFPI works like it
2139 nvmcntl.dspace := '1'; -- were MFPD
2140 else
2141 nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
2142 end if;
2143 nvmcntl.mode := PSW.pmode;
2144 nvmcntl.req := '1';
2145 nstate := s_opa_mfp_mem_w;
2146
2147 when s_opa_mfp_mem_w => -- -----------------------------------
2148 nstate := s_opa_mfp_mem_w;
2149 do_memcheck(nstate, nstatus, imemok);
2150 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
2151 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
2152 if imemok then
2153 ndpcntl.ddst_we := '1';
2154 nstate := s_opa_mfp_dec;
2155 end if;
2156
2157 when s_opa_mfp_dec => -- -----------------------------------
2158 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
2159 ndpcntl.ounit_const := "000000010";
2160 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
2161 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
2162 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2163 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
2164 ndpcntl.dsrc_we := '1'; -- update DSRC
2165 ndpcntl.gr_adst := c_gr_sp;
2166 ndpcntl.gr_we := '1'; -- update SP
2167 nmmumoni.regmod := '1';
2168 nmmumoni.isdec := '1';
2169 nstate := s_opa_mfp_push;
2170
2171 when s_opa_mfp_push => -- -----------------------------------
2172 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
2173 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
2174 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2175 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
2176 nvmcntl.dspace := '1';
2177 nvmcntl.kstack := is_kmode;
2178 nvmcntl.wacc := '1';
2179 nvmcntl.req := '1';
2180 nstate := s_opa_mfp_push_w;
2181
2182 when s_opa_mfp_push_w => -- -----------------------------------
2183 nstate := s_opa_mfp_push_w;
2184 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for cc)
2185 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0) (for cc)
2186 do_memcheck(nstate, nstatus, imemok);
2187 if imemok then
2188 ndpcntl.psr_ccwe := '1'; -- set cc (ounit via res_sel)
2189 idm_idone := '1'; -- instruction done
2190 do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
2191 end if;
2192
2193 -- trap and interrupt handling states --------------------------------------
2194
2195 when s_abort_4 => -- -----------------------------------
2196 lvector := "0000001"; -- vector (4)
2197 do_start_vec(nstate, ndpcntl, lvector);
2198
2199 when s_abort_10 => -- -----------------------------------
2200 idm_idone := '1'; -- instruction done
2201 lvector := "0000010"; -- vector (10)
2202 do_start_vec(nstate, ndpcntl, lvector);
2203
2204 when s_trap_disp => -- -----------------------------------
2205 if R_STATUS.treq_mmu = '1' then -- mmu trap requested ?
2206 lvector := "0101010"; -- mmu trap: vector (250)
2207 elsif R_STATUS.treq_ysv = '1' then -- ysv trap requested ?
2208 lvector := "0000001"; -- ysv trap: vector (4)
2209 ncpuerr.ysv := '1';
2210 nstatus.in_vecysv := '1'; -- signal start of ysv vector flow
2211 else
2212 lvector := "0000011"; -- trace trap: vector (14)
2213 end if;
2214 nstatus.treq_mmu := '0'; -- clear trap request flags
2215 nstatus.treq_ysv := '0'; --
2216 nstatus.treq_tbit := '0'; --
2217 do_start_vec(nstate, ndpcntl, lvector);
2218
2219 when s_int_ext => -- -----------------------------------
2220 lvector := R_STATUS.intvect; -- external vector
2221 do_start_vec(nstate, ndpcntl, lvector);
2222
2223 -- vector flow states ------------------------------------------------------
2224
2225 when s_vec_getpc => -- -----------------------------------
2226 nmmumoni.vstart := '1'; -- signal vstart
2227 nstatus.in_vecflow := '1'; -- signal vector flow
2228 nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
2229 do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_vec_getpc_w, nmmumoni);
2230
2231 when s_vec_getpc_w => -- -----------------------------------
2232 nstate := s_vec_getpc_w;
2233 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
2234 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
2235 do_memcheck(nstate, nstatus, imemok);
2236 if VM_STAT.err = '1' then -- in case of vm-err
2237 nstatus.cpugo := '0'; -- non-recoverable error
2238 nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
2239 nstate := s_idle;
2240 end if;
2241 if imemok then
2242 ndpcntl.ddst_we := '1'; -- DDST = new PC
2243 nstate := s_vec_getps;
2244 end if;
2245
2246 when s_vec_getps => -- -----------------------------------
2247 nvmcntl.mode := c_psw_kmode; -- fetch PS from kernel D space
2248 do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_vec_getps_w, nmmumoni);
2249
2250 when s_vec_getps_w => -- -----------------------------------
2251 nstate := s_vec_getps_w;
2252 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
2253 ndpcntl.psr_func := c_psr_func_wint; -- interupt mode write
2254 do_memcheck(nstate, nstatus, imemok);
2255 if VM_STAT.err = '1' then -- in case of vm-err
2256 nstatus.cpugo := '0'; -- non-recoverable error
2257 nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
2258 nstate := s_idle;
2259 end if;
2260 if imemok then
2261 ndpcntl.psr_we := '1'; -- store new PS
2262 nstate := s_vec_getsp;
2263 end if;
2264
2265 when s_vec_getsp => -- -----------------------------------
2266 ndpcntl.gr_asrc := c_gr_sp;
2267 ndpcntl.dsrc_we := '1'; -- DSRC = SP (in new mode)
2268 nstate := s_vec_decsp;
2269
2270 when s_vec_decsp => -- -----------------------------------
2271 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
2272 ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
2273 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
2274 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
2275 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2276 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
2277 ndpcntl.dsrc_we := '1'; -- update DSRC
2278 ndpcntl.gr_adst := c_gr_sp;
2279 ndpcntl.gr_we := '1'; -- update SP too
2280 nmmumoni.regmod := '1'; -- record vector push in MMR1
2281 nmmumoni.isdec := '1';
2282 nstate := s_vec_pushps;
2283
2284 when s_vec_pushps => -- -----------------------------------
2285 ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP (old PS)
2286 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
2287 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2288 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
2289 nvmcntl.wacc := '1'; -- write mem
2290 nvmcntl.dspace := '1';
2291 nvmcntl.kstack := is_kmode;
2292 nvmcntl.req := '1';
2293 nstate := s_vec_pushps_w;
2294
2295 when s_vec_pushps_w => -- -----------------------------------
2296 ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
2297 ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
2298 ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
2299 ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
2300 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2301 ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
2302 ndpcntl.gr_adst := c_gr_sp;
2303
2304 nstate := s_vec_pushps_w;
2305 do_memcheck(nstate, nstatus, imemok);
2306 if imemok then
2307 ndpcntl.dsrc_we := '1'; -- update DSRC
2308 ndpcntl.gr_we := '1'; -- update SP too
2309 nmmumoni.regmod := '1'; -- record vector push in MMR1
2310 nmmumoni.isdec := '1';
2311 nstate := s_vec_pushpc;
2312 end if;
2313
2314 when s_vec_pushpc => -- -----------------------------------
2315 ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
2316 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
2317 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2318 ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
2319 nvmcntl.wacc := '1'; -- write mem
2320 nvmcntl.dspace := '1';
2321 nvmcntl.kstack := is_kmode;
2322 nvmcntl.req := '1';
2323 nstate := s_vec_pushpc_w;
2324
2325 when s_vec_pushpc_w => -- -----------------------------------
2326 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
2327 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
2328 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2329 ndpcntl.gr_adst := c_gr_pc;
2330
2331 nstate := s_vec_pushpc_w;
2332 do_memcheck(nstate, nstatus, imemok);
2333 if imemok then
2334 nstatus.treq_tbit := PSW.tflag; -- copy PSW.tflag to treq_bit
2335 nstatus.in_vecflow := '0'; -- signal end vector flow
2336 nstatus.in_vecser := '0'; -- signal end of ser flow
2337 nstatus.in_vecysv := '0'; -- signal end of ysv flow
2338 ndpcntl.gr_we := '1'; -- load new PC
2339 idm_pcload := '1'; -- signal flow change
2340 do_fork_next(nstate, nstatus, nmmumoni); -- ???
2341 end if;
2342
2343 -- return from trap or interrupt handling states ----------------------------
2344
2345 when s_rti_getpc => -- -----------------------------------
2346 do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getpc_w,
2347 nmmumoni, pupdt_sp=>'1');
2348
2349 when s_rti_getpc_w => -- -----------------------------------
2350 nstate := s_rti_getpc_w;
2351 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
2352 ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
2353 do_memcheck(nstate, nstatus, imemok);
2354 if imemok then
2355 ndpcntl.ddst_we := '1'; -- DDST = new PC
2356 nstate := s_rti_getps;
2357 end if;
2358
2359 when s_rti_getps => -- -----------------------------------
2360 do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getps_w,
2361 nmmumoni, pupdt_sp=>'1');
2362
2363 when s_rti_getps_w => -- -----------------------------------
2364 nstate := s_rti_getps_w;
2365 do_memcheck(nstate, nstatus, imemok);
2366 ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
2367 if is_kmode = '1' then -- if in kernel mode
2368 ndpcntl.psr_func := c_psr_func_wall; -- write all fields
2369 else
2370 ndpcntl.psr_func := c_psr_func_wrti; -- otherwise filter
2371 end if;
2372 if imemok then
2373 ndpcntl.psr_we := '1'; -- load new PS
2374 nstate := s_rti_newpc;
2375 end if;
2376
2377 when s_rti_newpc => -- -----------------------------------
2378 if R_IDSTAT.op_rti = '1' then -- if RTI instruction
2379 nstatus.treq_tbit := PSW.tflag; -- copy PSW.tflag to treq_bit
2380 else -- else RTT
2381 nstatus.treq_tbit := '0'; -- no tbit trap
2382 end if;
2383 ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
2384 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
2385 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2386 ndpcntl.gr_adst := c_gr_pc;
2387 ndpcntl.gr_we := '1'; -- load new PC
2388 idm_pcload := '1'; -- signal flow change
2389 idm_idone := '1'; -- instruction done
2390 do_fork_next(nstate, nstatus, nmmumoni);
2391
2392 -- exception abort states ---------------------------------------------------
2393
2394 when s_vmerr => -- -----------------------------------
2395 nstate := s_cpufail;
2396
2397 -- setup for R_VMSTAT.err_ser='1'
2398 ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
2399 ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
2400 ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
2401 ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
2402 ndpcntl.gr_mode := c_psw_kmode; -- set kmode SP to 4
2403 ndpcntl.gr_adst := c_gr_sp;
2404
2405 nstatus.treq_mmu := '0'; -- cancel mmu trap request
2406 nstatus.treq_ysv := '0'; -- cancel ysv trap request
2407 nstatus.treq_tbit := '0'; -- cancel tbit trap request
2408
2409 if R_VMSTAT.fail = '1' then -- vmbox failure
2410 nstatus.cpugo := '0'; -- halt cpu
2411 nstatus.cpurust := c_cpurust_vfail;
2412 nstate := s_idle;
2413
2414 elsif R_STATUS.in_vecser = '1' then -- double fatal stack error
2415 nstatus.cpugo := '0'; -- give up, HALT cpu
2416 nstatus.cpurust := c_cpurust_recser;
2417 nstate := s_idle;
2418
2419 elsif R_VMSTAT.err = '1' then -- normal vm errors
2420 if R_VMSTAT.err_ser = '1' then
2421 nstatus.in_vecser := '1'; -- signal start of ser flow
2422 nstatus.in_vecysv := '0'; -- cancel ysv flow
2423 ndpcntl.gr_we := '1';
2424
2425 if R_VMSTAT.err_odd='1' then
2426 ncpuerr.oddadr := '1';
2427 elsif R_VMSTAT.err_nxm = '1' then
2428 ncpuerr.nxm := '1';
2429 elsif R_VMSTAT.err_iobto = '1' then
2430 ncpuerr.iobto := '1';
2431 elsif R_VMSTAT.err_rsv = '1' then
2432 ncpuerr.rsv := '1';
2433 end if;
2434 nstate := s_abort_4;
2435
2436 elsif R_VMSTAT.err_odd = '1' then
2437 ncpuerr.oddadr := '1';
2438 nstate := s_abort_4;
2439 elsif R_VMSTAT.err_nxm = '1' then
2440 ncpuerr.nxm := '1';
2441 nstate := s_abort_4;
2442 elsif R_VMSTAT.err_iobto = '1' then
2443 ncpuerr.iobto := '1';
2444 nstate := s_abort_4;
2445
2446 elsif R_VMSTAT.err_mmu = '1' then
2447 lvector := "0101010"; -- vector (250)
2448 do_start_vec(nstate, ndpcntl, lvector);
2449 end if;
2450 end if;
2451
2452 when s_cpufail => -- -----------------------------------
2453 nstatus.cpugo := '0';
2454 nstatus.cpurust := c_cpurust_sfail;
2455 nstate := s_idle;
2456
2457 when others => -- -----------------------------------
2458 nstate := s_cpufail;
2459
2460 end case;
2461
2462 if HBPT = '1' then -- handle hardware bpt
2463 nstatus.cpurust := c_cpurust_hbpt;
2464 nstatus.suspint :='1';
2465 end if;
2466 nstatus.suspext := ESUSP_I;
2467
2468 -- handle cpususp transitions
2469 if nstatus.suspint='1' or nstatus.suspext='1' then
2470 nstatus.cpususp := '1';
2471 elsif R_STATUS.suspint='0' and R_STATUS.suspext='0' then
2472 nstatus.cpususp := '0';
2473 end if;
2474
2475 if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test
2476 -- nstatus here !!
2477 nstatus.cmdbusy := '0';
2478 ndpcntl.cpdout_we := '1';
2479 end if;
2480
2481 N_STATE <= nstate;
2482 N_STATUS <= nstatus;
2483 N_CPUERR <= ncpuerr;
2484 N_IDSTAT <= nidstat;
2485
2486 INT_ACK <= R_STATUS.intack;
2487 CRESET <= R_STATUS.creset;
2488 BRESET <= R_STATUS.breset;
2489 ESUSP_O <= R_STATUS.suspint; -- FIXME_code: handle masking later
2490
2491 DP_CNTL <= ndpcntl;
2492 VM_CNTL <= nvmcntl;
2493 VM_CNTL_L <= nvmcntl;
2494
2495 nmmumoni.regnum := ndpcntl.gr_adst;
2496 nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
2497 MMU_MONI <= nmmumoni;
2498
2499 DM_STAT_SE.idle <= idm_idle;
2500 DM_STAT_SE.cpbusy <= idm_cpbusy;
2501 DM_STAT_SE.istart <= nmmumoni.istart;
2502 DM_STAT_SE.idec <= idm_idec;
2503 DM_STAT_SE.idone <= idm_idone;
2504 DM_STAT_SE.itimer <= R_STATUS.itimer;
2505 DM_STAT_SE.pcload <= idm_pcload;
2506 DM_STAT_SE.vstart <= nmmumoni.vstart;
2507
2508 end process proc_next;
2509
2510 proc_cpstat : process (R_STATUS)
2511 begin
2512 CP_STAT <= cp_stat_init;
2513 CP_STAT.cmdbusy <= R_STATUS.cmdbusy;
2514 CP_STAT.cmdack <= R_STATUS.cmdack;
2515 CP_STAT.cmderr <= R_STATUS.cmderr;
2516 CP_STAT.cmdmerr <= R_STATUS.cmdmerr;
2517 CP_STAT.cpugo <= R_STATUS.cpugo;
2518 CP_STAT.cpustep <= R_STATUS.cpustep;
2519 CP_STAT.cpuwait <= R_STATUS.cpuwait;
2520 CP_STAT.cpususp <= R_STATUS.cpususp;
2521 CP_STAT.cpurust <= R_STATUS.cpurust;
2522 CP_STAT.suspint <= R_STATUS.suspint;
2523 CP_STAT.suspext <= R_STATUS.suspext;
2524 end process proc_cpstat;
2525
2526 -- SNUM creation logic is conditional due to synthesis impact in vivado.
2527 -- SNUM = 'full state number' only available when dmscnt unit enabled.
2528 SNUM1 : if sys_conf_dmscnt generate
2529 begin
2530 proc_snum : process (R_STATE)
2531 variable isnum : slv8 := (others=>'0');
2532 begin
2533 isnum := (others=>'0');
2534 case R_STATE is
2535 -- STATE2SNUM mapper begin
2536 when s_idle => isnum := x"00";
2537 when s_cp_regread => isnum := x"01";
2538 when s_cp_rps => isnum := x"02";
2539 when s_cp_memr_w => isnum := x"03";
2540 when s_cp_memw_w => isnum := x"04";
2541 when s_ifetch => isnum := x"05";
2542 when s_ifetch_w => isnum := x"06";
2543 when s_idecode => isnum := x"07";
2544
2545 when s_srcr_def => isnum := x"08";
2546 when s_srcr_def_w => isnum := x"09";
2547 when s_srcr_inc => isnum := x"0a";
2548 when s_srcr_inc_w => isnum := x"0b";
2549 when s_srcr_dec => isnum := x"0c";
2550 when s_srcr_dec1 => isnum := x"0d";
2551 when s_srcr_ind => isnum := x"0e";
2552 when s_srcr_ind1_w => isnum := x"0f";
2553 when s_srcr_ind2 => isnum := x"10";
2554 when s_srcr_ind2_w => isnum := x"11";
2555
2556 when s_dstr_def => isnum := x"12";
2557 when s_dstr_def_w => isnum := x"13";
2558 when s_dstr_inc => isnum := x"14";
2559 when s_dstr_inc_w => isnum := x"15";
2560 when s_dstr_dec => isnum := x"16";
2561 when s_dstr_dec1 => isnum := x"17";
2562 when s_dstr_ind => isnum := x"18";
2563 when s_dstr_ind1_w => isnum := x"19";
2564 when s_dstr_ind2 => isnum := x"1a";
2565 when s_dstr_ind2_w => isnum := x"1b";
2566
2567 when s_dstw_def => isnum := x"1c";
2568 when s_dstw_def_w => isnum := x"1d";
2569 when s_dstw_inc => isnum := x"1e";
2570 when s_dstw_inc_w => isnum := x"1f";
2571 when s_dstw_incdef_w => isnum := x"20";
2572 when s_dstw_dec => isnum := x"21";
2573 when s_dstw_dec1 => isnum := x"22";
2574 when s_dstw_ind => isnum := x"23";
2575 when s_dstw_ind_w => isnum := x"24";
2576 when s_dstw_def246 => isnum := x"25";
2577
2578 when s_dsta_inc => isnum := x"26";
2579 when s_dsta_incdef_w => isnum := x"27";
2580 when s_dsta_dec => isnum := x"28";
2581 when s_dsta_dec1 => isnum := x"29";
2582 when s_dsta_ind => isnum := x"2a";
2583 when s_dsta_ind_w => isnum := x"2b";
2584
2585 when s_op_halt => isnum := x"2c";
2586 when s_op_wait => isnum := x"2d";
2587 when s_op_trap => isnum := x"2e";
2588 when s_op_reset => isnum := x"2f";
2589 when s_op_rts => isnum := x"30";
2590 when s_op_rts_pop => isnum := x"31";
2591 when s_op_rts_pop_w => isnum := x"32";
2592 when s_op_spl => isnum := x"33";
2593 when s_op_mcc => isnum := x"34";
2594 when s_op_br => isnum := x"35";
2595 when s_op_mark => isnum := x"36";
2596 when s_op_mark1 => isnum := x"37";
2597 when s_op_mark_pop => isnum := x"38";
2598 when s_op_mark_pop_w => isnum := x"39";
2599 when s_op_sob => isnum := x"3a";
2600 when s_op_sob1 => isnum := x"3b";
2601
2602 when s_opg_gen => isnum := x"3c";
2603 when s_opg_gen_rmw_w => isnum := x"3d";
2604 when s_opg_mul => isnum := x"3e";
2605 when s_opg_mul1 => isnum := x"3f";
2606 when s_opg_div => isnum := x"40";
2607 when s_opg_div_cn => isnum := x"41";
2608 when s_opg_div_cr => isnum := x"42";
2609 when s_opg_div_sq => isnum := x"43";
2610 when s_opg_div_sr => isnum := x"44";
2611 when s_opg_div_quit => isnum := x"45";
2612 when s_opg_ash => isnum := x"46";
2613 when s_opg_ash_cn => isnum := x"47";
2614 when s_opg_ashc => isnum := x"48";
2615 when s_opg_ashc_cn => isnum := x"49";
2616 when s_opg_ashc_wl => isnum := x"4a";
2617
2618 when s_opa_jsr => isnum := x"4b";
2619 when s_opa_jsr1 => isnum := x"4c";
2620 when s_opa_jsr_push => isnum := x"4d";
2621 when s_opa_jsr_push_w => isnum := x"4e";
2622 when s_opa_jsr2 => isnum := x"4f";
2623 when s_opa_jmp => isnum := x"50";
2624 when s_opa_mtp => isnum := x"51";
2625 when s_opa_mtp_pop_w => isnum := x"52";
2626 when s_opa_mtp_reg => isnum := x"53";
2627 when s_opa_mtp_mem => isnum := x"54";
2628 when s_opa_mtp_mem_w => isnum := x"55";
2629 when s_opa_mfp_reg => isnum := x"56";
2630 when s_opa_mfp_mem => isnum := x"57";
2631 when s_opa_mfp_mem_w => isnum := x"58";
2632 when s_opa_mfp_dec => isnum := x"59";
2633 when s_opa_mfp_push => isnum := x"5a";
2634 when s_opa_mfp_push_w => isnum := x"5b";
2635
2636 when s_abort_4 => isnum := x"5c";
2637 when s_abort_10 => isnum := x"5d";
2638 when s_trap_disp => isnum := x"5e";
2639
2640 when s_int_ext => isnum := x"5f";
2641
2642 when s_vec_getpc => isnum := x"60";
2643 when s_vec_getpc_w => isnum := x"61";
2644 when s_vec_getps => isnum := x"62";
2645 when s_vec_getps_w => isnum := x"63";
2646 when s_vec_getsp => isnum := x"64";
2647 when s_vec_decsp => isnum := x"65";
2648 when s_vec_pushps => isnum := x"66";
2649 when s_vec_pushps_w => isnum := x"67";
2650 when s_vec_pushpc => isnum := x"68";
2651 when s_vec_pushpc_w => isnum := x"69";
2652
2653 when s_rti_getpc => isnum := x"6a";
2654 when s_rti_getpc_w => isnum := x"6b";
2655 when s_rti_getps => isnum := x"6c";
2656 when s_rti_getps_w => isnum := x"6d";
2657 when s_rti_newpc => isnum := x"6e";
2658
2659 when s_vmerr => isnum := x"6f";
2660 when s_cpufail => isnum := x"70";
2661
2662 -- STATE2SNUM mapper end
2663 when others => isnum := x"ff";
2664 end case;
2665 DM_STAT_SE.snum <= isnum;
2666 end process proc_snum;
2667 end generate SNUM1;
2668
2669 -- if dmscnt not enable setup SNUM based on state categories (currently 4)
2670 -- and a 'wait' indicator determined from monitoring VM_CNTL and VM_STAT
2671 SNUM0 : if not sys_conf_dmscnt generate
2672 signal R_VMWAIT : slbit := '0'; -- vmwait flag
2673 begin
2674
2675 proc_vmwait: process (CLK)
2676 begin
2677 if rising_edge(CLK) then
2678 if GRESET = '1' then
2679 R_VMWAIT <= '0';
2680 else
2681 if VM_CNTL_L.req = '1' then
2682 R_VMWAIT <= '1';
2683 elsif VM_STAT.ack = '1' or VM_STAT.err = '1' or VM_STAT.fail='1' then
2684 R_VMWAIT <= '0';
2685 end if;
2686 end if;
2687 end if;
2688 end process proc_vmwait;
2689
2690 proc_snum : process (R_STATE, R_VMWAIT)
2691 variable isnum_con : slbit := '0';
2692 variable isnum_ins : slbit := '0';
2693 variable isnum_vec : slbit := '0';
2694 variable isnum_err : slbit := '0';
2695 begin
2696 isnum_con := '0';
2697 isnum_ins := '0';
2698 isnum_vec := '0';
2699 isnum_err := '0';
2700 case R_STATE is
2701 when s_idle => null;
2702 when s_cp_regread => isnum_con := '1';
2703 when s_cp_rps => isnum_con := '1';
2704 when s_cp_memr_w => isnum_con := '1';
2705 when s_cp_memw_w => isnum_con := '1';
2706 when s_ifetch => isnum_ins := '1';
2707 when s_ifetch_w => isnum_ins := '1';
2708 when s_idecode => isnum_ins := '1';
2709
2710 when s_srcr_def => isnum_ins := '1';
2711 when s_srcr_def_w => isnum_ins := '1';
2712 when s_srcr_inc => isnum_ins := '1';
2713 when s_srcr_inc_w => isnum_ins := '1';
2714 when s_srcr_dec => isnum_ins := '1';
2715 when s_srcr_dec1 => isnum_ins := '1';
2716 when s_srcr_ind => isnum_ins := '1';
2717 when s_srcr_ind1_w => isnum_ins := '1';
2718 when s_srcr_ind2 => isnum_ins := '1';
2719 when s_srcr_ind2_w => isnum_ins := '1';
2720
2721 when s_dstr_def => isnum_ins := '1';
2722 when s_dstr_def_w => isnum_ins := '1';
2723 when s_dstr_inc => isnum_ins := '1';
2724 when s_dstr_inc_w => isnum_ins := '1';
2725 when s_dstr_dec => isnum_ins := '1';
2726 when s_dstr_dec1 => isnum_ins := '1';
2727 when s_dstr_ind => isnum_ins := '1';
2728 when s_dstr_ind1_w => isnum_ins := '1';
2729 when s_dstr_ind2 => isnum_ins := '1';
2730 when s_dstr_ind2_w => isnum_ins := '1';
2731
2732 when s_dstw_def => isnum_ins := '1';
2733 when s_dstw_def_w => isnum_ins := '1';
2734 when s_dstw_inc => isnum_ins := '1';
2735 when s_dstw_inc_w => isnum_ins := '1';
2736 when s_dstw_incdef_w => isnum_ins := '1';
2737 when s_dstw_dec => isnum_ins := '1';
2738 when s_dstw_dec1 => isnum_ins := '1';
2739 when s_dstw_ind => isnum_ins := '1';
2740 when s_dstw_ind_w => isnum_ins := '1';
2741 when s_dstw_def246 => isnum_ins := '1';
2742
2743 when s_dsta_inc => isnum_ins := '1';
2744 when s_dsta_incdef_w => isnum_ins := '1';
2745 when s_dsta_dec => isnum_ins := '1';
2746 when s_dsta_dec1 => isnum_ins := '1';
2747 when s_dsta_ind => isnum_ins := '1';
2748 when s_dsta_ind_w => isnum_ins := '1';
2749
2750 when s_op_halt => isnum_ins := '1';
2751 when s_op_wait => isnum_ins := '1';
2752 when s_op_trap => isnum_ins := '1';
2753 when s_op_reset => isnum_ins := '1';
2754 when s_op_rts => isnum_ins := '1';
2755 when s_op_rts_pop => isnum_ins := '1';
2756 when s_op_rts_pop_w => isnum_ins := '1';
2757 when s_op_spl => isnum_ins := '1';
2758 when s_op_mcc => isnum_ins := '1';
2759 when s_op_br => isnum_ins := '1';
2760 when s_op_mark => isnum_ins := '1';
2761 when s_op_mark1 => isnum_ins := '1';
2762 when s_op_mark_pop => isnum_ins := '1';
2763 when s_op_mark_pop_w => isnum_ins := '1';
2764 when s_op_sob => isnum_ins := '1';
2765 when s_op_sob1 => isnum_ins := '1';
2766
2767 when s_opg_gen => isnum_ins := '1';
2768 when s_opg_gen_rmw_w => isnum_ins := '1';
2769 when s_opg_mul => isnum_ins := '1';
2770 when s_opg_mul1 => isnum_ins := '1';
2771 when s_opg_div => isnum_ins := '1';
2772 when s_opg_div_cn => isnum_ins := '1';
2773 when s_opg_div_cr => isnum_ins := '1';
2774 when s_opg_div_sq => isnum_ins := '1';
2775 when s_opg_div_sr => isnum_ins := '1';
2776 when s_opg_div_quit => isnum_ins := '1';
2777 when s_opg_ash => isnum_ins := '1';
2778 when s_opg_ash_cn => isnum_ins := '1';
2779 when s_opg_ashc => isnum_ins := '1';
2780 when s_opg_ashc_cn => isnum_ins := '1';
2781 when s_opg_ashc_wl => isnum_ins := '1';
2782
2783 when s_opa_jsr => isnum_ins := '1';
2784 when s_opa_jsr1 => isnum_ins := '1';
2785 when s_opa_jsr_push => isnum_ins := '1';
2786 when s_opa_jsr_push_w => isnum_ins := '1';
2787 when s_opa_jsr2 => isnum_ins := '1';
2788 when s_opa_jmp => isnum_ins := '1';
2789 when s_opa_mtp => isnum_ins := '1';
2790 when s_opa_mtp_pop_w => isnum_ins := '1';
2791 when s_opa_mtp_reg => isnum_ins := '1';
2792 when s_opa_mtp_mem => isnum_ins := '1';
2793 when s_opa_mtp_mem_w => isnum_ins := '1';
2794 when s_opa_mfp_reg => isnum_ins := '1';
2795 when s_opa_mfp_mem => isnum_ins := '1';
2796 when s_opa_mfp_mem_w => isnum_ins := '1';
2797 when s_opa_mfp_dec => isnum_ins := '1';
2798 when s_opa_mfp_push => isnum_ins := '1';
2799 when s_opa_mfp_push_w => isnum_ins := '1';
2800
2801 when s_abort_4 => isnum_ins := '1';
2802 when s_abort_10 => isnum_ins := '1';
2803 when s_trap_disp => isnum_ins := '1';
2804
2805 when s_int_ext => isnum_vec := '1';
2806
2807 when s_vec_getpc => isnum_vec := '1';
2808 when s_vec_getpc_w => isnum_vec := '1';
2809 when s_vec_getps => isnum_vec := '1';
2810 when s_vec_getps_w => isnum_vec := '1';
2811 when s_vec_getsp => isnum_vec := '1';
2812 when s_vec_decsp => isnum_vec := '1';
2813 when s_vec_pushps => isnum_vec := '1';
2814 when s_vec_pushps_w => isnum_vec := '1';
2815 when s_vec_pushpc => isnum_vec := '1';
2816 when s_vec_pushpc_w => isnum_vec := '1';
2817
2818 when s_rti_getpc => isnum_vec := '1';
2819 when s_rti_getpc_w => isnum_vec := '1';
2820 when s_rti_getps => isnum_vec := '1';
2821 when s_rti_getps_w => isnum_vec := '1';
2822 when s_rti_newpc => isnum_vec := '1';
2823
2824 when s_vmerr => isnum_err := '1';
2825 when s_cpufail => isnum_err := '1';
2826
2827 when others => null;
2828 end case;
2829
2830 DM_STAT_SE.snum <= (others=>'0');
2831 DM_STAT_SE.snum(c_snum_f_con) <= isnum_con;
2832 DM_STAT_SE.snum(c_snum_f_ins) <= isnum_ins;
2833 DM_STAT_SE.snum(c_snum_f_vec) <= isnum_vec;
2834 DM_STAT_SE.snum(c_snum_f_err) <= isnum_err;
2835 DM_STAT_SE.snum(c_snum_f_vmw) <= R_VMWAIT;
2836
2837 end process proc_snum;
2838 end generate SNUM0;
2839
2840end syn;
ib_sel
Definition: ib_sel.vhd:27
ib_sel.SEL
out SEL slbit
Definition: ib_sel.vhd:35
ib_sel.IB_ADDR
IB_ADDR slv16
Definition: ib_sel.vhd:29
ib_sel.CLK
in CLK slbit
Definition: ib_sel.vhd:32
ib_sel.IB_MREQ
in IB_MREQ ib_mreq_type
Definition: ib_sel.vhd:33
iblib
Definition: iblib.vhd:33
pdp11_sequencer.syn
Definition: pdp11_sequencer.vhd:130
pdp11_sequencer.syn.ibaddr_cpuerr
slv16 := slv( to_unsigned( 8#177766#, 16) ) ibaddr_cpuerr
Definition: pdp11_sequencer.vhd:132
pdp11_sequencer.syn.N_STATUS
cpustat_type := cpustat_init N_STATUS
Definition: pdp11_sequencer.vhd:276
pdp11_sequencer.syn.R_CPUERR
cpuerr_type := cpuerr_init R_CPUERR
Definition: pdp11_sequencer.vhd:277
pdp11_sequencer.syn.R_IDSTAT
decode_stat_type := decode_stat_init R_IDSTAT
Definition: pdp11_sequencer.vhd:280
pdp11_sequencer.syn.do_memread_srcinc
do_memread_srcincpnstate,pndpcntl,pnvmcntl,pwstate,pnmmumoni,pupdt_sp,
Definition: pdp11_sequencer.vhd:425
pdp11_sequencer.syn.do_memwrite
do_memwritepnstate,pnvmcntl,pwstate,pmacc,pispace,
Definition: pdp11_sequencer.vhd:450
pdp11_sequencer.syn.do_fork_dstr
do_fork_dstrpnstate,pidstat,
Definition: pdp11_sequencer.vhd:500
pdp11_sequencer.syn.cpuerr_ibf_oddadr
integer := 6 cpuerr_ibf_oddadr
Definition: pdp11_sequencer.vhd:135
pdp11_sequencer.syn.do_fork_opg
do_fork_opgpnstate,pidstat,
Definition: pdp11_sequencer.vhd:512
pdp11_sequencer.syn.R_VMSTAT
vm_stat_type := vm_stat_init R_VMSTAT
Definition: pdp11_sequencer.vhd:283
pdp11_sequencer.syn.do_fork_opa
do_fork_opapnstate,pidstat,
Definition: pdp11_sequencer.vhd:529
pdp11_sequencer.syn.cpuerr_ibf_ysv
integer := 3 cpuerr_ibf_ysv
Definition: pdp11_sequencer.vhd:138
pdp11_sequencer.syn.do_start_vec
do_start_vecpnstate,pndpcntl,pvector,
Definition: pdp11_sequencer.vhd:591
pdp11_sequencer.syn.cpuerr_ibf_iobto
integer := 4 cpuerr_ibf_iobto
Definition: pdp11_sequencer.vhd:137
pdp11_sequencer.syn.cpuerr_ibf_nxm
integer := 5 cpuerr_ibf_nxm
Definition: pdp11_sequencer.vhd:136
pdp11_sequencer.syn.do_fork_next_pref
do_fork_next_prefpnstate,pnstatus,pndpcntl,pnvmcntl,pnmmumoni,
Definition: pdp11_sequencer.vhd:563
pdp11_sequencer.syn.R_STATE
state_type := s_idle R_STATE
Definition: pdp11_sequencer.vhd:269
pdp11_sequencer.syn.do_memcheck
do_memcheckpnstate,pnstatus,pmok,
Definition: pdp11_sequencer.vhd:464
pdp11_sequencer.syn.fsm_encoding
string fsm_encoding
Definition: pdp11_sequencer.vhd:272
pdp11_sequencer.syn.do_memread_i
do_memread_ipnstate,pndpcntl,pnvmcntl,pwstate,
Definition: pdp11_sequencer.vhd:397
pdp11_sequencer.syn.do_memread_d
do_memread_dpnstate,pnvmcntl,pwstate,pbytop,pmacc,pispace,pkstack,
Definition: pdp11_sequencer.vhd:409
pdp11_sequencer.syn.state_type
(s_idle,s_cp_regread,s_cp_rps,s_cp_memr_w,s_cp_memw_w,s_ifetch,s_ifetch_w,s_idecode,s_srcr_def,s_srcr_def_w,s_srcr_inc,s_srcr_inc_w,s_srcr_dec,s_srcr_dec1,s_srcr_ind,s_srcr_ind1_w,s_srcr_ind2,s_srcr_ind2_w,s_dstr_def,s_dstr_def_w,s_dstr_inc,s_dstr_inc_w,s_dstr_dec,s_dstr_dec1,s_dstr_ind,s_dstr_ind1_w,s_dstr_ind2,s_dstr_ind2_w,s_dstw_def,s_dstw_def_w,s_dstw_inc,s_dstw_inc_w,s_dstw_incdef_w,s_dstw_dec,s_dstw_dec1,s_dstw_ind,s_dstw_ind_w,s_dstw_def246,s_dsta_inc,s_dsta_incdef_w,s_dsta_dec,s_dsta_dec1,s_dsta_ind,s_dsta_ind_w,s_op_halt,s_op_wait,s_op_trap,s_op_reset,s_op_rts,s_op_rts_pop,s_op_rts_pop_w,s_op_spl,s_op_mcc,s_op_br,s_op_mark,s_op_mark1,s_op_mark_pop,s_op_mark_pop_w,s_op_sob,s_op_sob1,s_opg_gen,s_opg_gen_rmw_w,s_opg_mul,s_opg_mul1,s_opg_div,s_opg_div_cn,s_opg_div_cr,s_opg_div_sq,s_opg_div_sr,s_opg_div_quit,s_opg_ash,s_opg_ash_cn,s_opg_ashc,s_opg_ashc_cn,s_opg_ashc_wl,s_opa_jsr,s_opa_jsr1,s_opa_jsr_push,s_opa_jsr_push_w,s_opa_jsr2,s_opa_jmp,s_opa_mtp,s_opa_mtp_pop_w,s_opa_mtp_reg,s_opa_mtp_mem,s_opa_mtp_mem_w,s_opa_mfp_reg,s_opa_mfp_mem,s_opa_mfp_mem_w,s_opa_mfp_dec,s_opa_mfp_push,s_opa_mfp_push_w,s_abort_4,s_abort_10,s_trap_disp,s_int_ext,s_vec_getpc,s_vec_getpc_w,s_vec_getps,s_vec_getps_w,s_vec_getsp,s_vec_decsp,s_vec_pushps,s_vec_pushps_w,s_vec_pushpc,s_vec_pushpc_w,s_rti_getpc,s_rti_getpc_w,s_rti_getps,s_rti_getps_w,s_rti_newpc,s_vmerr,s_cpufail) state_type
Definition: pdp11_sequencer.vhd:141
pdp11_sequencer.syn.N_CPUERR
cpuerr_type := cpuerr_init N_CPUERR
Definition: pdp11_sequencer.vhd:278
pdp11_sequencer.syn.cpuerr_ibf_illhlt
integer := 7 cpuerr_ibf_illhlt
Definition: pdp11_sequencer.vhd:134
pdp11_sequencer.syn.R_STATUS
cpustat_type := cpustat_init R_STATUS
Definition: pdp11_sequencer.vhd:275
pdp11_sequencer.syn.N_IDSTAT
decode_stat_type := decode_stat_init N_IDSTAT
Definition: pdp11_sequencer.vhd:281
pdp11_sequencer.syn.VM_CNTL_L
vm_cntl_type := vm_cntl_init VM_CNTL_L
Definition: pdp11_sequencer.vhd:287
pdp11_sequencer.syn.R_VMWAIT
slbit := '0' R_VMWAIT
Definition: pdp11_sequencer.vhd:2672
pdp11_sequencer.syn.N_STATE
state_type N_STATE
Definition: pdp11_sequencer.vhd:270
pdp11_sequencer.syn.cpuerr_ibf_rsv
integer := 2 cpuerr_ibf_rsv
Definition: pdp11_sequencer.vhd:139
pdp11_sequencer.syn.IBSEL_CPUERR
slbit := '0' IBSEL_CPUERR
Definition: pdp11_sequencer.vhd:285
pdp11_sequencer.syn.do_const_opsize
do_const_opsizepndpcntl,pbytop,pisdef,pregnum,
Definition: pdp11_sequencer.vhd:486
pdp11_sequencer.syn.do_fork_next
do_fork_nextpnstate,pnstatus,pnmmumoni,
Definition: pdp11_sequencer.vhd:542
pdp11_sequencer
Definition: pdp11_sequencer.vhd:102
pdp11_sequencer.INT_PRI
in INT_PRI slv3
Definition: pdp11_sequencer.vhd:112
pdp11_sequencer.ID_STAT
in ID_STAT decode_stat_type
Definition: pdp11_sequencer.vhd:108
pdp11_sequencer.DP_CNTL
out DP_CNTL dpath_cntl_type
Definition: pdp11_sequencer.vhd:118
pdp11_sequencer.PSW
in PSW psw_type
Definition: pdp11_sequencer.vhd:106
pdp11_sequencer.IREG
in IREG slv16
Definition: pdp11_sequencer.vhd:107
pdp11_sequencer.GRESET
in GRESET slbit
Definition: pdp11_sequencer.vhd:105
pdp11_sequencer.CLK
in CLK slbit
Definition: pdp11_sequencer.vhd:104
pdp11_sequencer.VM_STAT
in VM_STAT vm_stat_type
Definition: pdp11_sequencer.vhd:111
pdp11_sequencer.MMU_MONI
out MMU_MONI mmu_moni_type
Definition: pdp11_sequencer.vhd:117
pdp11_sequencer.IB_MREQ
in IB_MREQ ib_mreq_type
Definition: pdp11_sequencer.vhd:124
pdp11_sequencer.CRESET
out CRESET slbit
Definition: pdp11_sequencer.vhd:115
pdp11_sequencer.IB_SRES
out IB_SRES ib_sres_type
Definition: pdp11_sequencer.vhd:125
pdp11_sequencer.VM_CNTL
out VM_CNTL vm_cntl_type
Definition: pdp11_sequencer.vhd:119
pdp11_sequencer.CP_CNTL
in CP_CNTL cp_cntl_type
Definition: pdp11_sequencer.vhd:110
pdp11_sequencer.INT_ACK
out INT_ACK slbit
Definition: pdp11_sequencer.vhd:114
pdp11_sequencer.CP_STAT
out CP_STAT cp_stat_type
Definition: pdp11_sequencer.vhd:120
pdp11_sequencer.DM_STAT_SE
out DM_STAT_SE dm_stat_se_type
Definition: pdp11_sequencer.vhd:127
pdp11_sequencer.ESUSP_I
in ESUSP_I slbit
Definition: pdp11_sequencer.vhd:122
pdp11_sequencer.ESUSP_O
out ESUSP_O slbit
Definition: pdp11_sequencer.vhd:121
pdp11_sequencer.INT_VECT
in INT_VECT slv9_2
Definition: pdp11_sequencer.vhd:113
pdp11_sequencer.DP_STAT
in DP_STAT dpath_stat_type
Definition: pdp11_sequencer.vhd:109
pdp11_sequencer.BRESET
out BRESET slbit
Definition: pdp11_sequencer.vhd:116
pdp11_sequencer.HBPT
in HBPT slbit
Definition: pdp11_sequencer.vhd:123
pdp11
Definition: pdp11.vhd:123
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
slvtypes.slv3
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
slvtypes.slv9_2
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
slvtypes.slv2
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slvtypes.slv
std_logic_vector slv
Definition: slvtypes.vhd:31
sys_conf
Definition: sys_conf_sim.vhd:21