29use ieee.std_logic_1164.
all;
30use ieee.numeric_std.
all;
61 signal R_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
63 signal N_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
86 variable ssr1out : slv16 := (others=>'0');
87 variable ssr2out : slv16 := (others=>'0');
90 ssr1out := (others=>'0');
98 ssr2out := (others=>'0');
103 IB_SRES.dout <= ssr1out or ssr2out;
108 end process proc_ibres;
112 if rising_edge(CLK) then
116 end process proc_regs;
121 variable nssr1 : mmu_ssr1_type := mmu_ssr1_init;
122 variable nssr2 : slv16 := (others=>'0');
123 variable delta : slv5 := (others=>'0');
124 variable use_rb : slbit := '0';
130 delta := "0" & MONI.delta;
133 if MONI.regnum/=nssr1.ra_num and unsigned(nssr1.ra_delta)/=0 then
138 nssr1 := mmu_ssr1_init;
139 nssr2 := (others=>'0');
152 elsif TRACE = '1' then
154 if MONI.istart = '1' then
155 nssr1 := mmu_ssr1_init;
158 elsif MONI.regmod = '1' then
160 nssr1.ra_num := MONI.regnum;
161 if MONI.isdec = '0' then
162 nssr1.ra_delta := slv(signed(nssr1.ra_delta) + signed(delta));
164 nssr1.ra_delta := slv(signed(nssr1.ra_delta) - signed(delta));
167 nssr1.rb_num := MONI.regnum;
168 if MONI.isdec = '0' then
169 nssr1.rb_delta := slv(signed(nssr1.rb_delta) + signed(delta));
171 nssr1.rb_delta := slv(signed(nssr1.rb_delta) - signed(delta));
181 end process proc_comb;
integer range 15 downto 11 ssr1_ibf_rb_delta
slv16 :=( others => '0') R_SSR2
integer range 7 downto 3 ssr1_ibf_ra_delta
mmu_ssr1_type := mmu_ssr1_init R_SSR1
slv16 := slv( to_unsigned( 8#177576#, 16) ) ibaddr_ssr2
slv16 :=( others => '0') N_SSR2
integer range 2 downto 0 ssr1_ibf_ra_num
slv16 := slv( to_unsigned( 8#177574#, 16) ) ibaddr_ssr1
integer range 10 downto 8 ssr1_ibf_rb_num
mmu_ssr1_type := mmu_ssr1_init N_SSR1
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 15 downto 0) slv16