34use ieee.std_logic_1164.
all;
35use ieee.numeric_std.
all;
107 DI => IB_MREQ.din
(ibf_byte1
),
118 DI => IB_MREQ.din
(ibf_byte0
),
157 variable ibsel_dr : slbit := '0';
158 variable ibsel_ar : slbit := '0';
160 if rising_edge(CLK) then
177 end process proc_ibsel;
180 variable sarout : slv16 := (others=>'0');
181 variable sdrout : slv16 := (others=>'0');
184 sarout := (others=>'0');
189 sdrout := (others=>'0');
196 IB_SRES.dout <= sarout or sdrout;
201 end process proc_ibres;
210 variable eaddr : slv6 := (others=>'0');
211 variable idr : slbit := '0';
212 variable iar : slbit := '0';
220 eaddr(4) := not IB_MREQ.addr(6);
221 eaddr(3 downto 0) := IB_MREQ.addr(4 downto 1);
226 end process proc_eaddr;
276 end process proc_comb;
slv16 := slv( to_unsigned( 8#172200#, 16) ) ibaddr_smdar
slv16 := slv( to_unsigned( 8#177600#, 16) ) ibaddr_umdar
slv6 :=( others => '0') SADR_ADDR
slv16 := slv( to_unsigned( 8#172300#, 16) ) ibaddr_kmdar
integer range 7 downto 6 sdr_ibf_aib
slv7 :=( others => '0') SLF
integer range 3 downto 0 sdr_ibf_acf
integer range 14 downto 8 sdr_ibf_slf
slv16 :=( others => '0') SAF
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 6 downto 0) slv7
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 5 downto 0) slv6
std_logic_vector( 1 downto 0) slv2