ram_1swar_gen Entity Reference

Inheritance diagram for ram_1swar_gen:

Entities
syn	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
numeric_std
slvtypes	Package <slvtypes>
vcomponents

Generics
AWIDTH	positive := 4
DWIDTH	positive := 16

Ports
CLK	in	slbit
WE	in	slbit
ADDR	in	slv ( AWIDTH - 1 downto 0 )
DI	in	slv ( DWIDTH - 1 downto 0 )
DO	out	slv ( DWIDTH - 1 downto 0 )

Detailed Description

Definition at line 37 of file ram_1swar_gen.vhd.

Member Data Documentation

AWIDTH

AWIDTH positive := 4

Generic

Definition at line 39 of file ram_1swar_gen.vhd.

DWIDTH

DWIDTH positive := 16

Generic

Definition at line 40 of file ram_1swar_gen.vhd.

CLK

CLK in slbit

Port

Definition at line 42 of file ram_1swar_gen.vhd.

WE

WE in slbit

Port

Definition at line 43 of file ram_1swar_gen.vhd.

ADDR

ADDR in slv ( AWIDTH - 1 downto 0 )

Port

Definition at line 44 of file ram_1swar_gen.vhd.

DI

DI in slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 45 of file ram_1swar_gen.vhd.

DO

DO out slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 47 of file ram_1swar_gen.vhd.

ieee

ieee

Library

Definition at line 31 of file ram_1swar_gen.vhd.

std_logic_1164

std_logic_1164

use clause

Definition at line 32 of file ram_1swar_gen.vhd.

numeric_std

numeric_std

use clause

Definition at line 33 of file ram_1swar_gen.vhd.

slvtypes

slvtypes

use clause

Definition at line 35 of file ram_1swar_gen.vhd.

unisim

unisim

Library

Definition at line 25 of file ram_1swar_gen_unisim.vhd.

vcomponents

vcomponents

use clause

Definition at line 26 of file ram_1swar_gen_unisim.vhd.

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The documentation for this design unit was generated from the following files:

• vlib/memlib/ram_1swar_gen.vhd
• vlib/memlib/ram_1swar_gen_unisim.vhd