w11 - vhd 0.794
W11 CPU core and support modules
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iob_reg_i_gen.vhd
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1-- $Id: iob_reg_i_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: iob_reg_i_gen - syn
7-- Description: Registered IOB, input only, vector
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic Spartan, Virtex
12-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
13-- Revision History:
14-- Date Rev Version Comment
15-- 2007-12-16 101 1.0.1 add INIT generic port
16-- 2007-12-08 100 1.0 Initial version
17------------------------------------------------------------------------------
18
19library ieee;
20use ieee.std_logic_1164.all;
21
22use work.slvtypes.all;
23use work.xlib.all;
24
25entity iob_reg_i_gen is -- registered IOB, input, vector
26 generic (
27 DWIDTH : positive := 16; -- data port width
28 INIT : slbit := '0'); -- initial state
29 port (
30 CLK : in slbit; -- clock
31 CE : in slbit := '1'; -- clock enable
32 DI : out slv(DWIDTH-1 downto 0); -- input data
33 PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
34 );
36
37
38architecture syn of iob_reg_i_gen is
39
40 signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INIT);
41
42 attribute iob : string;
43 attribute iob of R_DI : signal is "true";
44
45begin
46
47 proc_regs: process (CLK)
48 begin
49 if rising_edge(CLK) then
50 if CE = '1' then
51 R_DI <= PAD;
52 end if;
53 end if;
54 end process proc_regs;
55
56 DI <= R_DI;
57
58end syn;
slv( DWIDTH- 1 downto 0) :=( others => INIT) R_DI
in CE slbit := '1'
in PAD slv( DWIDTH- 1 downto 0)
INIT slbit := '0'
in CLK slbit
out DI slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31
Definition: xlib.vhd:35