syn Architecture Reference

Architecture >> syn

Processes
proc_regs	( CLK )

Signals
R_DI	slv ( DWIDTH - 1 downto 0 ) := ( others = > INIT )

Attributes
iob	string
iob	signal is " true "

Detailed Description

Definition at line 38 of file iob_reg_i_gen.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs (   CLK   )

Process

Definition at line 47 of file iob_reg_i_gen.vhd.

Member Data Documentation

R_DI

R_DI slv ( DWIDTH - 1 downto 0 ) := ( others = > INIT )

Signal

Definition at line 40 of file iob_reg_i_gen.vhd.

iob [1/2]

iob string

Attribute

Definition at line 42 of file iob_reg_i_gen.vhd.

iob [2/2]

iob signal is " true "

Attribute

Definition at line 43 of file iob_reg_i_gen.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/xlib/iob_reg_i_gen.vhd