w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_stim 
proc_moni 
proc_memon 

Constants

clkmui_mul  positive := 6
clkmui_div  positive := 12
c_caco_wait  positive := 50
mwidth  positive := 2 ** sys_conf_bawidth
dwidth  positive := 8 * mwidth
clock_period  Delay_length := 12 . 5 ns
clock_offset  Delay_length := 200 ns
setup_time  Delay_length := 3 ns
c2out_time  Delay_length := 5 ns
sysclock_period  Delay_length := 5 . 833 ns
sysclock_offset  Delay_length := 200 ns

Signals

CLK  slbit := ' 0 '
RESET  slbit := ' 0 '
REQ  slbit := ' 0 '
WE  slbit := ' 0 '
BUSY  slbit := ' 0 '
ACK_R  slbit := ' 0 '
ACK_W  slbit := ' 0 '
ACT_R  slbit := ' 0 '
ACT_W  slbit := ' 0 '
ADDR  slv20 := ( others = > ' 0 ' )
BE  slv4 := ( others = > ' 0 ' )
DI  slv32 := ( others = > ' 0 ' )
DO  slv32 := ( others = > ' 0 ' )
MONI  sramif2migui_moni_type := sramif2migui_moni_init
SYS_CLK  slbit := ' 0 '
SYS_RST  slbit := ' 0 '
UI_CLK  slbit := ' 0 '
UI_CLK_SYNC_RST  slbit := ' 0 '
INIT_CALIB_COMPLETE  slbit := ' 0 '
APP_RDY  slbit := ' 0 '
APP_EN  slbit := ' 0 '
APP_CMD  slv3 := ( others = > ' 0 ' )
APP_ADDR  slv ( sys_conf_mawidth- 1 downto 0 ) := ( others = > ' 0 ' )
APP_WDF_RDY  slbit := ' 0 '
APP_WDF_WREN  slbit := ' 0 '
APP_WDF_DATA  slv ( dwidth - 1 downto 0 ) := ( others = > ' 0 ' )
APP_WDF_MASK  slv ( mwidth - 1 downto 0 ) := ( others = > ' 0 ' )
APP_WDF_END  slbit := ' 0 '
APP_RD_DATA_VALID  slbit := ' 0 '
APP_RD_DATA  slv ( dwidth - 1 downto 0 ) := ( others = > ' 0 ' )
APP_RD_DATA_END  slbit := ' 0 '
R_MEMON  slbit := ' 0 '
N_CHK_DATA  slbit := ' 0 '
N_REF_DATA  slv32 := ( others = > ' 0 ' )
N_REF_ADDR  slv20 := ( others = > ' 0 ' )
R_CHK_DATA_AL  slbit := ' 0 '
R_REF_DATA_AL  slv32 := ( others = > ' 0 ' )
R_REF_ADDR_AL  slv20 := ( others = > ' 0 ' )
R_CHK_DATA_DL  slbit := ' 0 '
R_REF_DATA_DL  slv32 := ( others = > ' 0 ' )
R_REF_ADDR_DL  slv20 := ( others = > ' 0 ' )
R_NRDRHIT  integer := 0
R_NWRRHIT  integer := 0
R_NWRFLUSH  integer := 0
R_NMIGCBUSY  integer := 0
R_NMIGWBUSY  integer := 0
R_NMIGCACOW  integer := 0
CLK_STOP  slbit := ' 0 '
CLK_CYCLE  integer := 0
UI_CLK_CYCLE  integer := 0

Instantiations

usrclkgen  simclk <Entity simclk>
sysclkgen  simclk <Entity simclk>
clkcnt  simclkcnt <Entity simclkcnt>
uiclkcnt  simclkcnt <Entity simclkcnt>
sr2mu  sramif2migui_core <Entity sramif2migui_core>
i0  migui_core_gsim <Entity migui_core_gsim>
i0  migui2bram <Entity migui2bram>

Detailed Description

Definition at line 40 of file tb_sramif2migui_core.vhd.

Member Function/Procedure/Process Documentation

◆ proc_stim()

proc_stim

Definition at line 237 of file tb_sramif2migui_core.vhd.

◆ proc_moni()

proc_moni ( )
Process

Definition at line 420 of file tb_sramif2migui_core.vhd.

◆ proc_memon()

proc_memon ( )
Process

Definition at line 482 of file tb_sramif2migui_core.vhd.

Member Data Documentation

◆ clkmui_mul

clkmui_mul positive := 6
Constant

Definition at line 42 of file tb_sramif2migui_core.vhd.

◆ clkmui_div

clkmui_div positive := 12
Constant

Definition at line 43 of file tb_sramif2migui_core.vhd.

◆ c_caco_wait

c_caco_wait positive := 50
Constant

Definition at line 45 of file tb_sramif2migui_core.vhd.

◆ mwidth

mwidth positive := 2 ** sys_conf_bawidth
Constant

Definition at line 47 of file tb_sramif2migui_core.vhd.

◆ dwidth

dwidth positive := 8 * mwidth
Constant

Definition at line 48 of file tb_sramif2migui_core.vhd.

◆ CLK

CLK slbit := ' 0 '
Signal

Definition at line 50 of file tb_sramif2migui_core.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 51 of file tb_sramif2migui_core.vhd.

◆ REQ

REQ slbit := ' 0 '
Signal

Definition at line 52 of file tb_sramif2migui_core.vhd.

◆ WE

WE slbit := ' 0 '
Signal

Definition at line 53 of file tb_sramif2migui_core.vhd.

◆ BUSY

BUSY slbit := ' 0 '
Signal

Definition at line 54 of file tb_sramif2migui_core.vhd.

◆ ACK_R

ACK_R slbit := ' 0 '
Signal

Definition at line 55 of file tb_sramif2migui_core.vhd.

◆ ACK_W

ACK_W slbit := ' 0 '
Signal

Definition at line 56 of file tb_sramif2migui_core.vhd.

◆ ACT_R

ACT_R slbit := ' 0 '
Signal

Definition at line 57 of file tb_sramif2migui_core.vhd.

◆ ACT_W

ACT_W slbit := ' 0 '
Signal

Definition at line 58 of file tb_sramif2migui_core.vhd.

◆ ADDR

ADDR slv20 := ( others = > ' 0 ' )
Signal

Definition at line 59 of file tb_sramif2migui_core.vhd.

◆ BE

BE slv4 := ( others = > ' 0 ' )
Signal

Definition at line 60 of file tb_sramif2migui_core.vhd.

◆ DI

DI slv32 := ( others = > ' 0 ' )
Signal

Definition at line 61 of file tb_sramif2migui_core.vhd.

◆ DO

DO slv32 := ( others = > ' 0 ' )
Signal

Definition at line 62 of file tb_sramif2migui_core.vhd.

◆ MONI

MONI sramif2migui_moni_type := sramif2migui_moni_init
Signal

Definition at line 63 of file tb_sramif2migui_core.vhd.

◆ SYS_CLK

SYS_CLK slbit := ' 0 '
Signal

Definition at line 65 of file tb_sramif2migui_core.vhd.

◆ SYS_RST

SYS_RST slbit := ' 0 '
Signal

Definition at line 66 of file tb_sramif2migui_core.vhd.

◆ UI_CLK

UI_CLK slbit := ' 0 '
Signal

Definition at line 68 of file tb_sramif2migui_core.vhd.

◆ UI_CLK_SYNC_RST

UI_CLK_SYNC_RST slbit := ' 0 '
Signal

Definition at line 69 of file tb_sramif2migui_core.vhd.

◆ INIT_CALIB_COMPLETE

INIT_CALIB_COMPLETE slbit := ' 0 '
Signal

Definition at line 70 of file tb_sramif2migui_core.vhd.

◆ APP_RDY

APP_RDY slbit := ' 0 '
Signal

Definition at line 71 of file tb_sramif2migui_core.vhd.

◆ APP_EN

APP_EN slbit := ' 0 '
Signal

Definition at line 72 of file tb_sramif2migui_core.vhd.

◆ APP_CMD

APP_CMD slv3 := ( others = > ' 0 ' )
Signal

Definition at line 73 of file tb_sramif2migui_core.vhd.

◆ APP_ADDR

APP_ADDR slv ( sys_conf_mawidth- 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 74 of file tb_sramif2migui_core.vhd.

◆ APP_WDF_RDY

APP_WDF_RDY slbit := ' 0 '
Signal

Definition at line 75 of file tb_sramif2migui_core.vhd.

◆ APP_WDF_WREN

APP_WDF_WREN slbit := ' 0 '
Signal

Definition at line 76 of file tb_sramif2migui_core.vhd.

◆ APP_WDF_DATA

APP_WDF_DATA slv ( dwidth - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 77 of file tb_sramif2migui_core.vhd.

◆ APP_WDF_MASK

APP_WDF_MASK slv ( mwidth - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 78 of file tb_sramif2migui_core.vhd.

◆ APP_WDF_END

APP_WDF_END slbit := ' 0 '
Signal

Definition at line 79 of file tb_sramif2migui_core.vhd.

◆ APP_RD_DATA_VALID

APP_RD_DATA_VALID slbit := ' 0 '
Signal

Definition at line 80 of file tb_sramif2migui_core.vhd.

◆ APP_RD_DATA

APP_RD_DATA slv ( dwidth - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 81 of file tb_sramif2migui_core.vhd.

◆ APP_RD_DATA_END

APP_RD_DATA_END slbit := ' 0 '
Signal

Definition at line 82 of file tb_sramif2migui_core.vhd.

◆ R_MEMON

R_MEMON slbit := ' 0 '
Signal

Definition at line 84 of file tb_sramif2migui_core.vhd.

◆ N_CHK_DATA

N_CHK_DATA slbit := ' 0 '
Signal

Definition at line 85 of file tb_sramif2migui_core.vhd.

◆ N_REF_DATA

N_REF_DATA slv32 := ( others = > ' 0 ' )
Signal

Definition at line 86 of file tb_sramif2migui_core.vhd.

◆ N_REF_ADDR

N_REF_ADDR slv20 := ( others = > ' 0 ' )
Signal

Definition at line 87 of file tb_sramif2migui_core.vhd.

◆ R_CHK_DATA_AL

R_CHK_DATA_AL slbit := ' 0 '
Signal

Definition at line 88 of file tb_sramif2migui_core.vhd.

◆ R_REF_DATA_AL

R_REF_DATA_AL slv32 := ( others = > ' 0 ' )
Signal

Definition at line 89 of file tb_sramif2migui_core.vhd.

◆ R_REF_ADDR_AL

R_REF_ADDR_AL slv20 := ( others = > ' 0 ' )
Signal

Definition at line 90 of file tb_sramif2migui_core.vhd.

◆ R_CHK_DATA_DL

R_CHK_DATA_DL slbit := ' 0 '
Signal

Definition at line 91 of file tb_sramif2migui_core.vhd.

◆ R_REF_DATA_DL

R_REF_DATA_DL slv32 := ( others = > ' 0 ' )
Signal

Definition at line 92 of file tb_sramif2migui_core.vhd.

◆ R_REF_ADDR_DL

R_REF_ADDR_DL slv20 := ( others = > ' 0 ' )
Signal

Definition at line 93 of file tb_sramif2migui_core.vhd.

◆ R_NRDRHIT

R_NRDRHIT integer := 0
Signal

Definition at line 95 of file tb_sramif2migui_core.vhd.

◆ R_NWRRHIT

R_NWRRHIT integer := 0
Signal

Definition at line 96 of file tb_sramif2migui_core.vhd.

◆ R_NWRFLUSH

R_NWRFLUSH integer := 0
Signal

Definition at line 97 of file tb_sramif2migui_core.vhd.

◆ R_NMIGCBUSY

R_NMIGCBUSY integer := 0
Signal

Definition at line 98 of file tb_sramif2migui_core.vhd.

◆ R_NMIGWBUSY

R_NMIGWBUSY integer := 0
Signal

Definition at line 99 of file tb_sramif2migui_core.vhd.

◆ R_NMIGCACOW

R_NMIGCACOW integer := 0
Signal

Definition at line 100 of file tb_sramif2migui_core.vhd.

◆ CLK_STOP

CLK_STOP slbit := ' 0 '
Signal

Definition at line 102 of file tb_sramif2migui_core.vhd.

◆ CLK_CYCLE

CLK_CYCLE integer := 0
Signal

Definition at line 103 of file tb_sramif2migui_core.vhd.

◆ UI_CLK_CYCLE

UI_CLK_CYCLE integer := 0
Signal

Definition at line 104 of file tb_sramif2migui_core.vhd.

◆ clock_period

clock_period Delay_length := 12 . 5 ns
Constant

Definition at line 106 of file tb_sramif2migui_core.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 107 of file tb_sramif2migui_core.vhd.

◆ setup_time

setup_time Delay_length := 3 ns
Constant

Definition at line 108 of file tb_sramif2migui_core.vhd.

◆ c2out_time

c2out_time Delay_length := 5 ns
Constant

Definition at line 109 of file tb_sramif2migui_core.vhd.

◆ sysclock_period

sysclock_period Delay_length := 5 . 833 ns
Constant

Definition at line 111 of file tb_sramif2migui_core.vhd.

◆ sysclock_offset

sysclock_offset Delay_length := 200 ns
Constant

Definition at line 112 of file tb_sramif2migui_core.vhd.

◆ usrclkgen

usrclkgen simclk
Instantiation

Definition at line 123 of file tb_sramif2migui_core.vhd.

◆ sysclkgen

sysclkgen simclk
Instantiation

Definition at line 132 of file tb_sramif2migui_core.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 134 of file tb_sramif2migui_core.vhd.

◆ uiclkcnt

uiclkcnt simclkcnt
Instantiation

Definition at line 135 of file tb_sramif2migui_core.vhd.

◆ sr2mu

sr2mu sramif2migui_core
Instantiation

Definition at line 171 of file tb_sramif2migui_core.vhd.

◆ i0 [1/2]

i0 migui_core_gsim
Instantiation

Definition at line 203 of file tb_sramif2migui_core.vhd.

◆ i0 [2/2]

i0 migui2bram
Instantiation

Definition at line 234 of file tb_sramif2migui_core.vhd.

The documentation for this design unit was generated from the following file: