w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_stim 
proc_moni 

Constants

clock_period  Delay_length := 20 ns
clock_offset  Delay_length := 200 ns
setup_time  Delay_length := 5 ns
c2out_time  Delay_length := 10 ns

Signals

CLK  slbit := ' 0 '
RESET  slbit := ' 0 '
CLKDIV  slv13 := slv ( to_unsigned ( 15 , 13 ) )
RXDATA  slv8 := ( others = > ' 0 ' )
RXVAL  slbit := ' 0 '
RXERR  slbit := ' 0 '
RXACT  slbit := ' 0 '
TXSD  slbit := ' 0 '
TXDATA  slv8 := ( others = > ' 0 ' )
TXENA  slbit := ' 0 '
TXBUSY  slbit := ' 0 '
CLK_STOP  slbit := ' 0 '
CLK_CYCLE  integer := 0
N_MON_VAL  slbit := ' 0 '
N_MON_DAT  slv8 := ( others = > ' 0 ' )
R_MON_VAL_1  slbit := ' 0 '
R_MON_DAT_1  slv8 := ( others = > ' 0 ' )
R_MON_VAL_2  slbit := ' 0 '
R_MON_DAT_2  slv8 := ( others = > ' 0 ' )

Instantiations

clkgen  simclk <Entity simclk>
clkcnt  simclkcnt <Entity simclkcnt>
uut  tbd_serport_uart_rxtx <Entity tbd_serport_uart_rxtx>

Detailed Description

Definition at line 49 of file tb_serport_uart_rxtx.vhd.

Member Function/Procedure/Process Documentation

◆ proc_stim()

proc_stim

Definition at line 108 of file tb_serport_uart_rxtx.vhd.

◆ proc_moni()

proc_moni ( )
Process

Definition at line 206 of file tb_serport_uart_rxtx.vhd.

Member Data Documentation

◆ CLK

CLK slbit := ' 0 '
Signal

Definition at line 51 of file tb_serport_uart_rxtx.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 52 of file tb_serport_uart_rxtx.vhd.

◆ CLKDIV

CLKDIV slv13 := slv ( to_unsigned ( 15 , 13 ) )
Signal

Definition at line 53 of file tb_serport_uart_rxtx.vhd.

◆ RXDATA

RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 54 of file tb_serport_uart_rxtx.vhd.

◆ RXVAL

RXVAL slbit := ' 0 '
Signal

Definition at line 55 of file tb_serport_uart_rxtx.vhd.

◆ RXERR

RXERR slbit := ' 0 '
Signal

Definition at line 56 of file tb_serport_uart_rxtx.vhd.

◆ RXACT

RXACT slbit := ' 0 '
Signal

Definition at line 57 of file tb_serport_uart_rxtx.vhd.

◆ TXSD

TXSD slbit := ' 0 '
Signal

Definition at line 58 of file tb_serport_uart_rxtx.vhd.

◆ TXDATA

TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 59 of file tb_serport_uart_rxtx.vhd.

◆ TXENA

TXENA slbit := ' 0 '
Signal

Definition at line 60 of file tb_serport_uart_rxtx.vhd.

◆ TXBUSY

TXBUSY slbit := ' 0 '
Signal

Definition at line 61 of file tb_serport_uart_rxtx.vhd.

◆ CLK_STOP

CLK_STOP slbit := ' 0 '
Signal

Definition at line 63 of file tb_serport_uart_rxtx.vhd.

◆ CLK_CYCLE

CLK_CYCLE integer := 0
Signal

Definition at line 64 of file tb_serport_uart_rxtx.vhd.

◆ N_MON_VAL

N_MON_VAL slbit := ' 0 '
Signal

Definition at line 66 of file tb_serport_uart_rxtx.vhd.

◆ N_MON_DAT

N_MON_DAT slv8 := ( others = > ' 0 ' )
Signal

Definition at line 67 of file tb_serport_uart_rxtx.vhd.

◆ R_MON_VAL_1

R_MON_VAL_1 slbit := ' 0 '
Signal

Definition at line 68 of file tb_serport_uart_rxtx.vhd.

◆ R_MON_DAT_1

R_MON_DAT_1 slv8 := ( others = > ' 0 ' )
Signal

Definition at line 69 of file tb_serport_uart_rxtx.vhd.

◆ R_MON_VAL_2

R_MON_VAL_2 slbit := ' 0 '
Signal

Definition at line 70 of file tb_serport_uart_rxtx.vhd.

◆ R_MON_DAT_2

R_MON_DAT_2 slv8 := ( others = > ' 0 ' )
Signal

Definition at line 71 of file tb_serport_uart_rxtx.vhd.

◆ clock_period

clock_period Delay_length := 20 ns
Constant

Definition at line 73 of file tb_serport_uart_rxtx.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 74 of file tb_serport_uart_rxtx.vhd.

◆ setup_time

setup_time Delay_length := 5 ns
Constant

Definition at line 75 of file tb_serport_uart_rxtx.vhd.

◆ c2out_time

c2out_time Delay_length := 10 ns
Constant

Definition at line 76 of file tb_serport_uart_rxtx.vhd.

◆ clkgen

clkgen simclk
Instantiation

Definition at line 87 of file tb_serport_uart_rxtx.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 89 of file tb_serport_uart_rxtx.vhd.

◆ uut

uut tbd_serport_uart_rxtx
Instantiation

Definition at line 105 of file tb_serport_uart_rxtx.vhd.

The documentation for this design unit was generated from the following file: