w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_stim 
proc_moni 
proc_memon 

Constants

clock_period  Delay_length := 20 ns
clock_offset  Delay_length := 200 ns
setup_time  Delay_length := 5 ns
c2out_time  Delay_length := 10 ns

Signals

CLK  slbit := ' 0 '
RESET  slbit := ' 0 '
REQ  slbit := ' 0 '
WE  slbit := ' 0 '
BUSY  slbit := ' 0 '
ACK_R  slbit := ' 0 '
ACK_W  slbit := ' 0 '
ACT_R  slbit := ' 0 '
ACT_W  slbit := ' 0 '
ADDR  slv18 := ( others = > ' 0 ' )
BE  slv4 := ( others = > ' 0 ' )
DI  slv32 := ( others = > ' 0 ' )
DO  slv32 := ( others = > ' 0 ' )
O_MEM_CE_N  slv2 := ( others = > ' 0 ' )
O_MEM_BE_N  slv4 := ( others = > ' 0 ' )
O_MEM_WE_N  slbit := ' 0 '
O_MEM_OE_N  slbit := ' 0 '
O_MEM_ADDR  slv18 := ( others = > ' 0 ' )
IO_MEM_DATA  slv32 := ( others = > ' 0 ' )
R_MEMON  slbit := ' 0 '
N_CHK_DATA  slbit := ' 0 '
N_REF_DATA  slv32 := ( others = > ' 0 ' )
N_REF_ADDR  slv18 := ( others = > ' 0 ' )
R_CHK_DATA_AL  slbit := ' 0 '
R_REF_DATA_AL  slv32 := ( others = > ' 0 ' )
R_REF_ADDR_AL  slv18 := ( others = > ' 0 ' )
R_CHK_DATA_DL  slbit := ' 0 '
R_REF_DATA_DL  slv32 := ( others = > ' 0 ' )
R_REF_ADDR_DL  slv18 := ( others = > ' 0 ' )
CLK_STOP  slbit := ' 0 '
CLK_CYCLE  integer := 0

Instantiations

clkgen  simclk <Entity simclk>
clkcnt  simclkcnt <Entity simclkcnt>
mem_l  is61lv25616al <Entity is61lv25616al>
mem_u  is61lv25616al <Entity is61lv25616al>
uut  s3_sram_memctl <Entity s3_sram_memctl>

Detailed Description

Definition at line 48 of file tb_s3_sram_memctl.vhd.

Member Function/Procedure/Process Documentation

◆ proc_stim()

proc_stim

Definition at line 147 of file tb_s3_sram_memctl.vhd.

◆ proc_moni()

proc_moni ( )
Process

Definition at line 276 of file tb_s3_sram_memctl.vhd.

◆ proc_memon()

proc_memon ( )
Process

Definition at line 318 of file tb_s3_sram_memctl.vhd.

Member Data Documentation

◆ CLK

CLK slbit := ' 0 '
Signal

Definition at line 50 of file tb_s3_sram_memctl.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 51 of file tb_s3_sram_memctl.vhd.

◆ REQ

REQ slbit := ' 0 '
Signal

Definition at line 52 of file tb_s3_sram_memctl.vhd.

◆ WE

WE slbit := ' 0 '
Signal

Definition at line 53 of file tb_s3_sram_memctl.vhd.

◆ BUSY

BUSY slbit := ' 0 '
Signal

Definition at line 54 of file tb_s3_sram_memctl.vhd.

◆ ACK_R

ACK_R slbit := ' 0 '
Signal

Definition at line 55 of file tb_s3_sram_memctl.vhd.

◆ ACK_W

ACK_W slbit := ' 0 '
Signal

Definition at line 56 of file tb_s3_sram_memctl.vhd.

◆ ACT_R

ACT_R slbit := ' 0 '
Signal

Definition at line 57 of file tb_s3_sram_memctl.vhd.

◆ ACT_W

ACT_W slbit := ' 0 '
Signal

Definition at line 58 of file tb_s3_sram_memctl.vhd.

◆ ADDR

ADDR slv18 := ( others = > ' 0 ' )
Signal

Definition at line 59 of file tb_s3_sram_memctl.vhd.

◆ BE

BE slv4 := ( others = > ' 0 ' )
Signal

Definition at line 60 of file tb_s3_sram_memctl.vhd.

◆ DI

DI slv32 := ( others = > ' 0 ' )
Signal

Definition at line 61 of file tb_s3_sram_memctl.vhd.

◆ DO

DO slv32 := ( others = > ' 0 ' )
Signal

Definition at line 62 of file tb_s3_sram_memctl.vhd.

◆ O_MEM_CE_N

O_MEM_CE_N slv2 := ( others = > ' 0 ' )
Signal

Definition at line 63 of file tb_s3_sram_memctl.vhd.

◆ O_MEM_BE_N

O_MEM_BE_N slv4 := ( others = > ' 0 ' )
Signal

Definition at line 64 of file tb_s3_sram_memctl.vhd.

◆ O_MEM_WE_N

O_MEM_WE_N slbit := ' 0 '
Signal

Definition at line 65 of file tb_s3_sram_memctl.vhd.

◆ O_MEM_OE_N

O_MEM_OE_N slbit := ' 0 '
Signal

Definition at line 66 of file tb_s3_sram_memctl.vhd.

◆ O_MEM_ADDR

O_MEM_ADDR slv18 := ( others = > ' 0 ' )
Signal

Definition at line 67 of file tb_s3_sram_memctl.vhd.

◆ IO_MEM_DATA

IO_MEM_DATA slv32 := ( others = > ' 0 ' )
Signal

Definition at line 68 of file tb_s3_sram_memctl.vhd.

◆ R_MEMON

R_MEMON slbit := ' 0 '
Signal

Definition at line 70 of file tb_s3_sram_memctl.vhd.

◆ N_CHK_DATA

N_CHK_DATA slbit := ' 0 '
Signal

Definition at line 71 of file tb_s3_sram_memctl.vhd.

◆ N_REF_DATA

N_REF_DATA slv32 := ( others = > ' 0 ' )
Signal

Definition at line 72 of file tb_s3_sram_memctl.vhd.

◆ N_REF_ADDR

N_REF_ADDR slv18 := ( others = > ' 0 ' )
Signal

Definition at line 73 of file tb_s3_sram_memctl.vhd.

◆ R_CHK_DATA_AL

R_CHK_DATA_AL slbit := ' 0 '
Signal

Definition at line 74 of file tb_s3_sram_memctl.vhd.

◆ R_REF_DATA_AL

R_REF_DATA_AL slv32 := ( others = > ' 0 ' )
Signal

Definition at line 75 of file tb_s3_sram_memctl.vhd.

◆ R_REF_ADDR_AL

R_REF_ADDR_AL slv18 := ( others = > ' 0 ' )
Signal

Definition at line 76 of file tb_s3_sram_memctl.vhd.

◆ R_CHK_DATA_DL

R_CHK_DATA_DL slbit := ' 0 '
Signal

Definition at line 77 of file tb_s3_sram_memctl.vhd.

◆ R_REF_DATA_DL

R_REF_DATA_DL slv32 := ( others = > ' 0 ' )
Signal

Definition at line 78 of file tb_s3_sram_memctl.vhd.

◆ R_REF_ADDR_DL

R_REF_ADDR_DL slv18 := ( others = > ' 0 ' )
Signal

Definition at line 79 of file tb_s3_sram_memctl.vhd.

◆ CLK_STOP

CLK_STOP slbit := ' 0 '
Signal

Definition at line 81 of file tb_s3_sram_memctl.vhd.

◆ CLK_CYCLE

CLK_CYCLE integer := 0
Signal

Definition at line 82 of file tb_s3_sram_memctl.vhd.

◆ clock_period

clock_period Delay_length := 20 ns
Constant

Definition at line 84 of file tb_s3_sram_memctl.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 85 of file tb_s3_sram_memctl.vhd.

◆ setup_time

setup_time Delay_length := 5 ns
Constant

Definition at line 86 of file tb_s3_sram_memctl.vhd.

◆ c2out_time

c2out_time Delay_length := 10 ns
Constant

Definition at line 87 of file tb_s3_sram_memctl.vhd.

◆ clkgen

clkgen simclk
Instantiation

Definition at line 98 of file tb_s3_sram_memctl.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 100 of file tb_s3_sram_memctl.vhd.

◆ mem_l

mem_l 61lv25616al
Instantiation

Definition at line 111 of file tb_s3_sram_memctl.vhd.

◆ mem_u

mem_u 61lv25616al
Instantiation

Definition at line 122 of file tb_s3_sram_memctl.vhd.

◆ uut

uut s3_sram_memctl
Instantiation

Definition at line 145 of file tb_s3_sram_memctl.vhd.

The documentation for this design unit was generated from the following file: