w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_fx2_mux  ( R_PORTSEL_FX2 , TBC_RXDATA , TBC_RXVAL , UART_TXBUSY , RTS_N , UART_RXDATA , UART_RXVAL , FX2_RXBUSY , FX2_TXDATA , FX2_TXVAL )
proc_ser_mux  ( R_PORTSEL_SER , UART_TXD , CTS_N , O_TXD , O_FUSP_TXD , O_FUSP_RTS_N )
proc_moni 
proc_simbus  ( SB_VAL )

Constants

sbaddr_portsel  slv8 := slv ( to_unsigned ( 8 , 8 ) )
clock_period  Delay_length := 20 ns
clock_offset  Delay_length := 200 ns

Signals

CLKOSC  slbit := ' 0 '
CLKCOM  slbit := ' 0 '
CLKCOM_CYCLE  integer := 0
RESET  slbit := ' 0 '
CLKDIV  slv2 := " 00 "
TBC_RXDATA  slv8 := ( others = > ' 0 ' )
TBC_RXVAL  slbit := ' 0 '
TBC_RXHOLD  slbit := ' 0 '
TBC_TXDATA  slv8 := ( others = > ' 0 ' )
TBC_TXENA  slbit := ' 0 '
UART_RXDATA  slv8 := ( others = > ' 0 ' )
UART_RXVAL  slbit := ' 0 '
UART_RXERR  slbit := ' 0 '
UART_RXACT  slbit := ' 0 '
UART_TXDATA  slv8 := ( others = > ' 0 ' )
UART_TXENA  slbit := ' 0 '
UART_TXBUSY  slbit := ' 0 '
FX2_RXDATA  slv8 := ( others = > ' 0 ' )
FX2_RXENA  slbit := ' 0 '
FX2_RXBUSY  slbit := ' 0 '
FX2_TXDATA  slv8 := ( others = > ' 0 ' )
FX2_TXVAL  slbit := ' 0 '
I_RXD  slbit := ' 1 '
O_TXD  slbit := ' 1 '
I_SWI  slv8 := ( others = > ' 0 ' )
I_BTN  slv4 := ( others = > ' 0 ' )
O_LED  slv8 := ( others = > ' 0 ' )
O_ANO_N  slv4 := ( others = > ' 0 ' )
O_SEG_N  slv8 := ( others = > ' 0 ' )
O_MEM_CE_N  slbit := ' 1 '
O_MEM_BE_N  slv2 := ( others = > ' 1 ' )
O_MEM_WE_N  slbit := ' 1 '
O_MEM_OE_N  slbit := ' 1 '
O_MEM_ADV_N  slbit := ' 1 '
O_MEM_CLK  slbit := ' 0 '
O_MEM_CRE  slbit := ' 0 '
I_MEM_WAIT  slbit := ' 0 '
O_MEM_ADDR  slv23 := ( others = > ' Z ' )
IO_MEM_DATA  slv16 := ( others = > ' 0 ' )
O_FLA_CE_N  slbit := ' 0 '
O_FUSP_RTS_N  slbit := ' 0 '
I_FUSP_CTS_N  slbit := ' 0 '
I_FUSP_RXD  slbit := ' 1 '
O_FUSP_TXD  slbit := ' 1 '
I_FX2_IFCLK  slbit := ' 0 '
O_FX2_FIFO  slv2 := ( others = > ' 0 ' )
I_FX2_FLAG  slv4 := ( others = > ' 0 ' )
O_FX2_SLRD_N  slbit := ' 1 '
O_FX2_SLWR_N  slbit := ' 1 '
O_FX2_SLOE_N  slbit := ' 1 '
O_FX2_PKTEND_N  slbit := ' 1 '
IO_FX2_DATA  slv8 := ( others = > ' Z ' )
UART_RESET  slbit := ' 0 '
UART_RXD  slbit := ' 1 '
UART_TXD  slbit := ' 1 '
CTS_N  slbit := ' 0 '
RTS_N  slbit := ' 0 '
R_PORTSEL_SER  slbit := ' 0 '
R_PORTSEL_XON  slbit := ' 0 '
R_PORTSEL_FX2  slbit := ' 0 '

Instantiations

clkgen  simclk <Entity simclk>
dcm_com  dcm_sfs <Entity dcm_sfs>
clkcnt  simclkcnt <Entity simclkcnt>
tbcore  tbcore_rlink <Entity tbcore_rlink>
n2core  tb_nexys2_core <Entity tb_nexys2_core>
uut  nexys2_fusp_cuff_aif
sermstr  serport_master_tb <Entity serport_master_tb>
fx2  fx2_2fifo_core <Entity fx2_2fifo_core>

Detailed Description

Definition at line 50 of file tb_nexys2_fusp_cuff.vhd.

Member Function/Procedure/Process Documentation

◆ proc_fx2_mux()

proc_fx2_mux (   R_PORTSEL_FX2,
  TBC_RXDATA,
  TBC_RXVAL,
  UART_TXBUSY,
  RTS_N,
  UART_RXDATA,
  UART_RXVAL,
  FX2_RXBUSY,
  FX2_TXDATA,
  FX2_TXVAL 
)

Definition at line 254 of file tb_nexys2_fusp_cuff.vhd.

◆ proc_ser_mux()

proc_ser_mux (   R_PORTSEL_SER ,
  UART_TXD ,
  CTS_N ,
  O_TXD ,
  O_FUSP_TXD ,
  O_FUSP_RTS_N  
)
Process

Definition at line 276 of file tb_nexys2_fusp_cuff.vhd.

◆ proc_moni()

proc_moni ( )
Process

Definition at line 296 of file tb_nexys2_fusp_cuff.vhd.

◆ proc_simbus()

proc_simbus (   SB_VAL  
)
Process

Definition at line 312 of file tb_nexys2_fusp_cuff.vhd.

Member Data Documentation

◆ CLKOSC

CLKOSC slbit := ' 0 '
Signal

Definition at line 52 of file tb_nexys2_fusp_cuff.vhd.

◆ CLKCOM

CLKCOM slbit := ' 0 '
Signal

Definition at line 53 of file tb_nexys2_fusp_cuff.vhd.

◆ CLKCOM_CYCLE

CLKCOM_CYCLE integer := 0
Signal

Definition at line 55 of file tb_nexys2_fusp_cuff.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 57 of file tb_nexys2_fusp_cuff.vhd.

◆ CLKDIV

CLKDIV slv2 := " 00 "
Signal

Definition at line 58 of file tb_nexys2_fusp_cuff.vhd.

◆ TBC_RXDATA

TBC_RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 60 of file tb_nexys2_fusp_cuff.vhd.

◆ TBC_RXVAL

TBC_RXVAL slbit := ' 0 '
Signal

Definition at line 61 of file tb_nexys2_fusp_cuff.vhd.

◆ TBC_RXHOLD

TBC_RXHOLD slbit := ' 0 '
Signal

Definition at line 62 of file tb_nexys2_fusp_cuff.vhd.

◆ TBC_TXDATA

TBC_TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 63 of file tb_nexys2_fusp_cuff.vhd.

◆ TBC_TXENA

TBC_TXENA slbit := ' 0 '
Signal

Definition at line 64 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_RXDATA

UART_RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 66 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_RXVAL

UART_RXVAL slbit := ' 0 '
Signal

Definition at line 67 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_RXERR

UART_RXERR slbit := ' 0 '
Signal

Definition at line 68 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_RXACT

UART_RXACT slbit := ' 0 '
Signal

Definition at line 69 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_TXDATA

UART_TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 70 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_TXENA

UART_TXENA slbit := ' 0 '
Signal

Definition at line 71 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_TXBUSY

UART_TXBUSY slbit := ' 0 '
Signal

Definition at line 72 of file tb_nexys2_fusp_cuff.vhd.

◆ FX2_RXDATA

FX2_RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 74 of file tb_nexys2_fusp_cuff.vhd.

◆ FX2_RXENA

FX2_RXENA slbit := ' 0 '
Signal

Definition at line 75 of file tb_nexys2_fusp_cuff.vhd.

◆ FX2_RXBUSY

FX2_RXBUSY slbit := ' 0 '
Signal

Definition at line 76 of file tb_nexys2_fusp_cuff.vhd.

◆ FX2_TXDATA

FX2_TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 77 of file tb_nexys2_fusp_cuff.vhd.

◆ FX2_TXVAL

FX2_TXVAL slbit := ' 0 '
Signal

Definition at line 78 of file tb_nexys2_fusp_cuff.vhd.

◆ I_RXD

I_RXD slbit := ' 1 '
Signal

Definition at line 80 of file tb_nexys2_fusp_cuff.vhd.

◆ O_TXD

O_TXD slbit := ' 1 '
Signal

Definition at line 81 of file tb_nexys2_fusp_cuff.vhd.

◆ I_SWI

I_SWI slv8 := ( others = > ' 0 ' )
Signal

Definition at line 82 of file tb_nexys2_fusp_cuff.vhd.

◆ I_BTN

I_BTN slv4 := ( others = > ' 0 ' )
Signal

Definition at line 83 of file tb_nexys2_fusp_cuff.vhd.

◆ O_LED

O_LED slv8 := ( others = > ' 0 ' )
Signal

Definition at line 84 of file tb_nexys2_fusp_cuff.vhd.

◆ O_ANO_N

O_ANO_N slv4 := ( others = > ' 0 ' )
Signal

Definition at line 85 of file tb_nexys2_fusp_cuff.vhd.

◆ O_SEG_N

O_SEG_N slv8 := ( others = > ' 0 ' )
Signal

Definition at line 86 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_CE_N

O_MEM_CE_N slbit := ' 1 '
Signal

Definition at line 88 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_BE_N

O_MEM_BE_N slv2 := ( others = > ' 1 ' )
Signal

Definition at line 89 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_WE_N

O_MEM_WE_N slbit := ' 1 '
Signal

Definition at line 90 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_OE_N

O_MEM_OE_N slbit := ' 1 '
Signal

Definition at line 91 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_ADV_N

O_MEM_ADV_N slbit := ' 1 '
Signal

Definition at line 92 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_CLK

O_MEM_CLK slbit := ' 0 '
Signal

Definition at line 93 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_CRE

O_MEM_CRE slbit := ' 0 '
Signal

Definition at line 94 of file tb_nexys2_fusp_cuff.vhd.

◆ I_MEM_WAIT

I_MEM_WAIT slbit := ' 0 '
Signal

Definition at line 95 of file tb_nexys2_fusp_cuff.vhd.

◆ O_MEM_ADDR

O_MEM_ADDR slv23 := ( others = > ' Z ' )
Signal

Definition at line 96 of file tb_nexys2_fusp_cuff.vhd.

◆ IO_MEM_DATA

IO_MEM_DATA slv16 := ( others = > ' 0 ' )
Signal

Definition at line 97 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FLA_CE_N

O_FLA_CE_N slbit := ' 0 '
Signal

Definition at line 98 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FUSP_RTS_N

O_FUSP_RTS_N slbit := ' 0 '
Signal

Definition at line 100 of file tb_nexys2_fusp_cuff.vhd.

◆ I_FUSP_CTS_N

I_FUSP_CTS_N slbit := ' 0 '
Signal

Definition at line 101 of file tb_nexys2_fusp_cuff.vhd.

◆ I_FUSP_RXD

I_FUSP_RXD slbit := ' 1 '
Signal

Definition at line 102 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FUSP_TXD

O_FUSP_TXD slbit := ' 1 '
Signal

Definition at line 103 of file tb_nexys2_fusp_cuff.vhd.

◆ I_FX2_IFCLK

I_FX2_IFCLK slbit := ' 0 '
Signal

Definition at line 105 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FX2_FIFO

O_FX2_FIFO slv2 := ( others = > ' 0 ' )
Signal

Definition at line 106 of file tb_nexys2_fusp_cuff.vhd.

◆ I_FX2_FLAG

I_FX2_FLAG slv4 := ( others = > ' 0 ' )
Signal

Definition at line 107 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FX2_SLRD_N

O_FX2_SLRD_N slbit := ' 1 '
Signal

Definition at line 108 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FX2_SLWR_N

O_FX2_SLWR_N slbit := ' 1 '
Signal

Definition at line 109 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FX2_SLOE_N

O_FX2_SLOE_N slbit := ' 1 '
Signal

Definition at line 110 of file tb_nexys2_fusp_cuff.vhd.

◆ O_FX2_PKTEND_N

O_FX2_PKTEND_N slbit := ' 1 '
Signal

Definition at line 111 of file tb_nexys2_fusp_cuff.vhd.

◆ IO_FX2_DATA

IO_FX2_DATA slv8 := ( others = > ' Z ' )
Signal

Definition at line 112 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_RESET

UART_RESET slbit := ' 0 '
Signal

Definition at line 114 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_RXD

UART_RXD slbit := ' 1 '
Signal

Definition at line 115 of file tb_nexys2_fusp_cuff.vhd.

◆ UART_TXD

UART_TXD slbit := ' 1 '
Signal

Definition at line 116 of file tb_nexys2_fusp_cuff.vhd.

◆ CTS_N

CTS_N slbit := ' 0 '
Signal

Definition at line 117 of file tb_nexys2_fusp_cuff.vhd.

◆ RTS_N

RTS_N slbit := ' 0 '
Signal

Definition at line 118 of file tb_nexys2_fusp_cuff.vhd.

◆ R_PORTSEL_SER

R_PORTSEL_SER slbit := ' 0 '
Signal

Definition at line 120 of file tb_nexys2_fusp_cuff.vhd.

◆ R_PORTSEL_XON

R_PORTSEL_XON slbit := ' 0 '
Signal

Definition at line 121 of file tb_nexys2_fusp_cuff.vhd.

◆ R_PORTSEL_FX2

R_PORTSEL_FX2 slbit := ' 0 '
Signal

Definition at line 122 of file tb_nexys2_fusp_cuff.vhd.

◆ sbaddr_portsel

sbaddr_portsel slv8 := slv ( to_unsigned ( 8 , 8 ) )
Constant

Definition at line 124 of file tb_nexys2_fusp_cuff.vhd.

◆ clock_period

clock_period Delay_length := 20 ns
Constant

Definition at line 126 of file tb_nexys2_fusp_cuff.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 127 of file tb_nexys2_fusp_cuff.vhd.

◆ clkgen

clkgen simclk
Instantiation

Definition at line 137 of file tb_nexys2_fusp_cuff.vhd.

◆ dcm_com

dcm_com dcm_sfs
Instantiation

Definition at line 148 of file tb_nexys2_fusp_cuff.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 150 of file tb_nexys2_fusp_cuff.vhd.

◆ tbcore

tbcore tbcore_rlink
Instantiation

Definition at line 160 of file tb_nexys2_fusp_cuff.vhd.

◆ n2core

n2core tb_nexys2_core
Instantiation

Definition at line 176 of file tb_nexys2_fusp_cuff.vhd.

◆ uut

uut nexys2_fusp_cuff_aif
Instantiation

Definition at line 211 of file tb_nexys2_fusp_cuff.vhd.

◆ sermstr

sermstr serport_master_tb
Instantiation

Definition at line 233 of file tb_nexys2_fusp_cuff.vhd.

◆ fx2

fx2 fx2_2fifo_core
Instantiation

Definition at line 252 of file tb_nexys2_fusp_cuff.vhd.

The documentation for this design unit was generated from the following file: