w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_stim 
proc_moni 

Constants

clock_period  Delay_length := 20 ns
clock_offset  Delay_length := 200 ns
setup_time  Delay_length := 5 ns
c2out_time  Delay_length := 10 ns

Signals

CLK  slbit := ' 0 '
RESET  slbit := ' 0 '
CE  slbit := ' 0 '
WE  slbit := ' 0 '
DI  slv16 := ( others = > ' 0 ' )
DO  slv16 := ( others = > ' 0 ' )
EMPTY  slbit := ' 0 '
FULL  slbit := ' 0 '
SIZE  slv4 := ( others = > ' 0 ' )
N_EMPTY  slbit := ' 1 '
N_FULL  slbit := ' 0 '
N_SIZE  slv4 := ( others = > ' 0 ' )
R_EMPTY  slbit := ' 1 '
R_FULL  slbit := ' 0 '
R_SIZE  slv4 := ( others = > ' 0 ' )
CLK_STOP  slbit := ' 0 '
CLK_CYCLE  integer := 0

Instantiations

clkgen  simclk <Entity simclk>
clkcnt  simclkcnt <Entity simclkcnt>
uut  tbd_fifo_simple_dram <Entity tbd_fifo_simple_dram>

Detailed Description

Definition at line 34 of file tb_fifo_simple_dram.vhd.

Member Function/Procedure/Process Documentation

◆ proc_stim()

proc_stim

Definition at line 88 of file tb_fifo_simple_dram.vhd.

◆ proc_moni()

proc_moni ( )
Process

Definition at line 203 of file tb_fifo_simple_dram.vhd.

Member Data Documentation

◆ CLK

CLK slbit := ' 0 '
Signal

Definition at line 36 of file tb_fifo_simple_dram.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 37 of file tb_fifo_simple_dram.vhd.

◆ CE

CE slbit := ' 0 '
Signal

Definition at line 38 of file tb_fifo_simple_dram.vhd.

◆ WE

WE slbit := ' 0 '
Signal

Definition at line 39 of file tb_fifo_simple_dram.vhd.

◆ DI

DI slv16 := ( others = > ' 0 ' )
Signal

Definition at line 40 of file tb_fifo_simple_dram.vhd.

◆ DO

DO slv16 := ( others = > ' 0 ' )
Signal

Definition at line 41 of file tb_fifo_simple_dram.vhd.

◆ EMPTY

EMPTY slbit := ' 0 '
Signal

Definition at line 42 of file tb_fifo_simple_dram.vhd.

◆ FULL

FULL slbit := ' 0 '
Signal

Definition at line 43 of file tb_fifo_simple_dram.vhd.

◆ SIZE

SIZE slv4 := ( others = > ' 0 ' )
Signal

Definition at line 44 of file tb_fifo_simple_dram.vhd.

◆ N_EMPTY

N_EMPTY slbit := ' 1 '
Signal

Definition at line 46 of file tb_fifo_simple_dram.vhd.

◆ N_FULL

N_FULL slbit := ' 0 '
Signal

Definition at line 47 of file tb_fifo_simple_dram.vhd.

◆ N_SIZE

N_SIZE slv4 := ( others = > ' 0 ' )
Signal

Definition at line 48 of file tb_fifo_simple_dram.vhd.

◆ R_EMPTY

R_EMPTY slbit := ' 1 '
Signal

Definition at line 49 of file tb_fifo_simple_dram.vhd.

◆ R_FULL

R_FULL slbit := ' 0 '
Signal

Definition at line 50 of file tb_fifo_simple_dram.vhd.

◆ R_SIZE

R_SIZE slv4 := ( others = > ' 0 ' )
Signal

Definition at line 51 of file tb_fifo_simple_dram.vhd.

◆ CLK_STOP

CLK_STOP slbit := ' 0 '
Signal

Definition at line 53 of file tb_fifo_simple_dram.vhd.

◆ CLK_CYCLE

CLK_CYCLE integer := 0
Signal

Definition at line 54 of file tb_fifo_simple_dram.vhd.

◆ clock_period

clock_period Delay_length := 20 ns
Constant

Definition at line 56 of file tb_fifo_simple_dram.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 57 of file tb_fifo_simple_dram.vhd.

◆ setup_time

setup_time Delay_length := 5 ns
Constant

Definition at line 58 of file tb_fifo_simple_dram.vhd.

◆ c2out_time

c2out_time Delay_length := 10 ns
Constant

Definition at line 59 of file tb_fifo_simple_dram.vhd.

◆ clkgen

clkgen simclk
Instantiation

Definition at line 70 of file tb_fifo_simple_dram.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 72 of file tb_fifo_simple_dram.vhd.

◆ uut

uut tbd_fifo_simple_dram
Instantiation

Definition at line 85 of file tb_fifo_simple_dram.vhd.

The documentation for this design unit was generated from the following file: