w11 - vhd 0.794
W11 CPU core and support modules
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Instantiations | Processes | Shared Variables | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_stim 
proc_moni 
proc_clkr  ( CLKR )

Signals

CLKW  slbit := ' 0 '
CLKR  slbit := ' 0 '
RESETW  slbit := ' 0 '
RESETR  slbit := ' 0 '
DI  slv16 := ( others = > ' 0 ' )
ENA  slbit := ' 0 '
BUSY  slbit := ' 0 '
DO  slv16 := ( others = > ' 0 ' )
VAL  slbit := ' 0 '
SIZEW  slv4 := ( others = > ' 0 ' )
SIZER  slv4 := ( others = > ' 0 ' )
N_HOLD  slbit := ' 0 '
R_HOLD  slbit := ' 0 '
CLKW_PERIOD  Delay_length := 20 ns
CLKR_PERIOD  Delay_length := 20 ns
CLK_HOLD  slbit := ' 1 '
CLK_STOP  slbit := ' 0 '
CLKW_CYCLE  integer := 0
CLKR_CYCLE  integer := 0
CLKR_C2OUT  Delay_length := 10 ns

Shared Variables

sv_nrstr  shared integer := := 0
sv_ndatar  shared integer := := 0

Instantiations

clkwgen  simclkv <Entity simclkv>
clkwcnt  simclkcnt <Entity simclkcnt>
clkrgen  simclkv <Entity simclkv>
clkrcnt  simclkcnt <Entity simclkcnt>
uut  tbd_fifo_2c_dram <Entity tbd_fifo_2c_dram>

Detailed Description

Definition at line 40 of file tb_fifo_2c_dram.vhd.

Member Function/Procedure/Process Documentation

◆ proc_stim()

proc_stim

Definition at line 108 of file tb_fifo_2c_dram.vhd.

◆ proc_moni()

proc_moni ( )
Process

Definition at line 258 of file tb_fifo_2c_dram.vhd.

◆ proc_clkr()

proc_clkr (   CLKR  
)
Process

Definition at line 317 of file tb_fifo_2c_dram.vhd.

Member Data Documentation

◆ CLKW

CLKW slbit := ' 0 '
Signal

Definition at line 42 of file tb_fifo_2c_dram.vhd.

◆ CLKR

CLKR slbit := ' 0 '
Signal

Definition at line 43 of file tb_fifo_2c_dram.vhd.

◆ RESETW

RESETW slbit := ' 0 '
Signal

Definition at line 44 of file tb_fifo_2c_dram.vhd.

◆ RESETR

RESETR slbit := ' 0 '
Signal

Definition at line 45 of file tb_fifo_2c_dram.vhd.

◆ DI

DI slv16 := ( others = > ' 0 ' )
Signal

Definition at line 46 of file tb_fifo_2c_dram.vhd.

◆ ENA

ENA slbit := ' 0 '
Signal

Definition at line 47 of file tb_fifo_2c_dram.vhd.

◆ BUSY

BUSY slbit := ' 0 '
Signal

Definition at line 48 of file tb_fifo_2c_dram.vhd.

◆ DO

DO slv16 := ( others = > ' 0 ' )
Signal

Definition at line 49 of file tb_fifo_2c_dram.vhd.

◆ VAL

VAL slbit := ' 0 '
Signal

Definition at line 50 of file tb_fifo_2c_dram.vhd.

◆ SIZEW

SIZEW slv4 := ( others = > ' 0 ' )
Signal

Definition at line 51 of file tb_fifo_2c_dram.vhd.

◆ SIZER

SIZER slv4 := ( others = > ' 0 ' )
Signal

Definition at line 52 of file tb_fifo_2c_dram.vhd.

◆ N_HOLD

N_HOLD slbit := ' 0 '
Signal

Definition at line 54 of file tb_fifo_2c_dram.vhd.

◆ R_HOLD

R_HOLD slbit := ' 0 '
Signal

Definition at line 55 of file tb_fifo_2c_dram.vhd.

◆ CLKW_PERIOD

CLKW_PERIOD Delay_length := 20 ns
Signal

Definition at line 57 of file tb_fifo_2c_dram.vhd.

◆ CLKR_PERIOD

CLKR_PERIOD Delay_length := 20 ns
Signal

Definition at line 58 of file tb_fifo_2c_dram.vhd.

◆ CLK_HOLD

CLK_HOLD slbit := ' 1 '
Signal

Definition at line 59 of file tb_fifo_2c_dram.vhd.

◆ CLK_STOP

CLK_STOP slbit := ' 0 '
Signal

Definition at line 60 of file tb_fifo_2c_dram.vhd.

◆ CLKW_CYCLE

CLKW_CYCLE integer := 0
Signal

Definition at line 61 of file tb_fifo_2c_dram.vhd.

◆ CLKR_CYCLE

CLKR_CYCLE integer := 0
Signal

Definition at line 62 of file tb_fifo_2c_dram.vhd.

◆ CLKR_C2OUT

CLKR_C2OUT Delay_length := 10 ns
Signal

Definition at line 64 of file tb_fifo_2c_dram.vhd.

◆ sv_nrstr

sv_nrstr shared integer := := 0
Shared Variable

Definition at line 66 of file tb_fifo_2c_dram.vhd.

◆ sv_ndatar

sv_ndatar shared integer := := 0
Shared Variable

Definition at line 67 of file tb_fifo_2c_dram.vhd.

◆ clkwgen

clkwgen simclkv
Instantiation

Definition at line 77 of file tb_fifo_2c_dram.vhd.

◆ clkwcnt

clkwcnt simclkcnt
Instantiation

Definition at line 79 of file tb_fifo_2c_dram.vhd.

◆ clkrgen

clkrgen simclkv
Instantiation

Definition at line 87 of file tb_fifo_2c_dram.vhd.

◆ clkrcnt

clkrcnt simclkcnt
Instantiation

Definition at line 89 of file tb_fifo_2c_dram.vhd.

◆ uut

uut tbd_fifo_2c_dram
Instantiation

Definition at line 105 of file tb_fifo_2c_dram.vhd.

The documentation for this design unit was generated from the following file: