w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Records | Signals
syn Architecture Reference
Architecture >> syn

Processes

proc_regw  ( CLKW )
proc_nextw  ( R_REGW , RESETW , ENA , R_REGR , RADDR , RADDR_S_BIN , WADDR_BIN )
proc_regr  ( CLKR )
proc_nextr  ( R_REGR , RESETR , HOLD , R_REGW , WADDR , WADDR_S_BIN , RADDR_BIN )

Constants

regw_init  regw_type := ( slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' )
regr_init  regr_type := ( slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' )

Signals

R_REGW  regw_type := regw_init
N_REGW  regw_type := regw_init
R_REGR  regr_type := regr_init
N_REGR  regr_type := regr_init
WADDR  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
RADDR  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
WADDR_BIN  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
RADDR_BIN  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
WADDR_S_BIN  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
RADDR_S_BIN  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
GCW_RST  slbit := ' 0 '
GCW_CE  slbit := ' 0 '
GCR_RST  slbit := ' 0 '
GCR_CE  slbit := ' 0 '

Records

regw_type 
raddr_c slv ( AWIDTH - 1 downto 0 )
raddr_s slv ( AWIDTH - 1 downto 0 )
sizew slv ( AWIDTH - 1 downto 0 )
busy slbit
rstw slbit
rstw_sc slbit
rstw_ss slbit
rstr_c slbit
rstr_s slbit
regr_type 
waddr_c slv ( AWIDTH - 1 downto 0 )
waddr_s slv ( AWIDTH - 1 downto 0 )
sizer slv ( AWIDTH - 1 downto 0 )
val slbit
rstr slbit
rstr_sc slbit
rstr_ss slbit
rstw_c slbit
rstw_s slbit

Instantiations

ram  ram_1swar_1ar_gen <Entity ram_1swar_1ar_gen>
gcw  gray_cnt_gen <Entity gray_cnt_gen>
gcr  gray_cnt_gen <Entity gray_cnt_gen>
g2b_ww  gray2bin_gen <Entity gray2bin_gen>
g2b_wr  gray2bin_gen <Entity gray2bin_gen>
g2b_rr  gray2bin_gen <Entity gray2bin_gen>
g2b_rw  gray2bin_gen <Entity gray2bin_gen>

Detailed Description

Definition at line 68 of file fifo_2c_dram.vhd.

Member Function/Procedure/Process Documentation

◆ proc_regw()

proc_regw (   CLKW)

Definition at line 181 of file fifo_2c_dram.vhd.

◆ proc_nextw()

proc_nextw (   R_REGW ,
  RESETW ,
  ENA ,
  R_REGR ,
  RADDR ,
  RADDR_S_BIN ,
  WADDR_BIN  
)
Process

Definition at line 188 of file fifo_2c_dram.vhd.

◆ proc_regr()

proc_regr (   CLKR  
)
Process

Definition at line 259 of file fifo_2c_dram.vhd.

◆ proc_nextr()

proc_nextr (   R_REGR ,
  RESETR ,
  HOLD ,
  R_REGW ,
  WADDR ,
  WADDR_S_BIN ,
  RADDR_BIN  
)
Process

Definition at line 266 of file fifo_2c_dram.vhd.

Member Data Documentation

◆ regw_type

regw_type
Record

Definition at line 70 of file fifo_2c_dram.vhd.

◆ raddr_c

raddr_c slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 71 of file fifo_2c_dram.vhd.

◆ raddr_s

raddr_s slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 72 of file fifo_2c_dram.vhd.

◆ sizew

sizew slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 73 of file fifo_2c_dram.vhd.

◆ busy

busy slbit
Record

Definition at line 74 of file fifo_2c_dram.vhd.

◆ rstw

rstw slbit
Record

Definition at line 75 of file fifo_2c_dram.vhd.

◆ rstw_sc

rstw_sc slbit
Record

Definition at line 76 of file fifo_2c_dram.vhd.

◆ rstw_ss

rstw_ss slbit
Record

Definition at line 77 of file fifo_2c_dram.vhd.

◆ rstr_c

rstr_c slbit
Record

Definition at line 78 of file fifo_2c_dram.vhd.

◆ rstr_s

rstr_s slbit
Record

Definition at line 79 of file fifo_2c_dram.vhd.

◆ regw_init

regw_init regw_type := ( slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' )
Constant

Definition at line 82 of file fifo_2c_dram.vhd.

◆ regr_type

regr_type
Record

Definition at line 91 of file fifo_2c_dram.vhd.

◆ waddr_c

waddr_c slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 92 of file fifo_2c_dram.vhd.

◆ waddr_s

waddr_s slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 93 of file fifo_2c_dram.vhd.

◆ sizer

sizer slv ( AWIDTH - 1 downto 0 )
Record

Definition at line 94 of file fifo_2c_dram.vhd.

◆ val

val slbit
Record

Definition at line 95 of file fifo_2c_dram.vhd.

◆ rstr

rstr slbit
Record

Definition at line 96 of file fifo_2c_dram.vhd.

◆ rstr_sc

rstr_sc slbit
Record

Definition at line 97 of file fifo_2c_dram.vhd.

◆ rstr_ss

rstr_ss slbit
Record

Definition at line 98 of file fifo_2c_dram.vhd.

◆ rstw_c

rstw_c slbit
Record

Definition at line 99 of file fifo_2c_dram.vhd.

◆ rstw_s

rstw_s slbit
Record

Definition at line 100 of file fifo_2c_dram.vhd.

◆ regr_init

regr_init regr_type := ( slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , slv ( to_unsigned ( 0 , AWIDTH ) ) , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' , ' 0 ' )
Constant

Definition at line 103 of file fifo_2c_dram.vhd.

◆ R_REGW

R_REGW regw_type := regw_init
Signal

Definition at line 112 of file fifo_2c_dram.vhd.

◆ N_REGW

N_REGW regw_type := regw_init
Signal

Definition at line 113 of file fifo_2c_dram.vhd.

◆ R_REGR

R_REGR regr_type := regr_init
Signal

Definition at line 114 of file fifo_2c_dram.vhd.

◆ N_REGR

N_REGR regr_type := regr_init
Signal

Definition at line 115 of file fifo_2c_dram.vhd.

◆ WADDR

WADDR slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 117 of file fifo_2c_dram.vhd.

◆ RADDR

RADDR slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 118 of file fifo_2c_dram.vhd.

◆ WADDR_BIN

WADDR_BIN slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 119 of file fifo_2c_dram.vhd.

◆ RADDR_BIN

RADDR_BIN slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 120 of file fifo_2c_dram.vhd.

◆ WADDR_S_BIN

WADDR_S_BIN slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 121 of file fifo_2c_dram.vhd.

◆ RADDR_S_BIN

RADDR_S_BIN slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 122 of file fifo_2c_dram.vhd.

◆ GCW_RST

GCW_RST slbit := ' 0 '
Signal

Definition at line 124 of file fifo_2c_dram.vhd.

◆ GCW_CE

GCW_CE slbit := ' 0 '
Signal

Definition at line 125 of file fifo_2c_dram.vhd.

◆ GCR_RST

GCR_RST slbit := ' 0 '
Signal

Definition at line 126 of file fifo_2c_dram.vhd.

◆ GCR_CE

GCR_CE slbit := ' 0 '
Signal

Definition at line 127 of file fifo_2c_dram.vhd.

◆ ram

ram ram_1swar_1ar_gen
Instantiation

Definition at line 143 of file fifo_2c_dram.vhd.

◆ gcw

gcw gray_cnt_gen
Instantiation

Definition at line 153 of file fifo_2c_dram.vhd.

◆ gcr

gcr gray_cnt_gen
Instantiation

Definition at line 163 of file fifo_2c_dram.vhd.

◆ g2b_ww

g2b_ww gray2bin_gen
Instantiation

Definition at line 167 of file fifo_2c_dram.vhd.

◆ g2b_wr

g2b_wr gray2bin_gen
Instantiation

Definition at line 170 of file fifo_2c_dram.vhd.

◆ g2b_rr

g2b_rr gray2bin_gen
Instantiation

Definition at line 173 of file fifo_2c_dram.vhd.

◆ g2b_rw

g2b_rw gray2bin_gen
Instantiation

Definition at line 176 of file fifo_2c_dram.vhd.

The documentation for this design unit was generated from the following file: