w11 - vhd 0.794
W11 CPU core and support modules
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Attributes | Instantiations | Processes | Signals | Subtypes
syn Architecture Reference
Architecture >> syn

Processes

proc_regw  ( CLKW )
proc_nextw  ( RW_BUSY , RW_SIZEW , RW_RSTW , RW_RSTW_E_S1 , RW_RSTR_S1 , ENA , RESETW , RADDR_BIN_W , WADDR_BIN_W )
proc_regr  ( CLKR )
proc_nextr  ( RR_VAL , RR_SIZER , RR_RSTR , RR_RSTR_E_S1 , RR_RSTW_S1 , HOLD , RESETR , RADDR_BIN_R , WADDR_BIN_R )

Subtypes

a_range  integer range AWIDTH - 1 downto 0

Signals

RW_RADDR_S0  slv ( a_range ) := ( others = > ' 0 ' )
RW_RADDR_S1  slv ( a_range ) := ( others = > ' 0 ' )
RW_SIZEW  slv ( a_range ) := ( others = > ' 0 ' )
RW_BUSY  slbit := ' 0 '
RW_RSTW  slbit := ' 0 '
RW_RSTW_E_S0  slbit := ' 0 '
RW_RSTW_E_S1  slbit := ' 0 '
RW_RSTR_S0  slbit := ' 0 '
RW_RSTR_S1  slbit := ' 0 '
NW_SIZEW  slv ( a_range ) := ( others = > ' 0 ' )
NW_BUSY  slbit := ' 0 '
NW_RSTW  slbit := ' 0 '
RR_WADDR_S0  slv ( a_range ) := ( others = > ' 0 ' )
RR_WADDR_S1  slv ( a_range ) := ( others = > ' 0 ' )
RR_SIZER  slv ( a_range ) := ( others = > ' 0 ' )
RR_VAL  slbit := ' 0 '
RR_RSTR  slbit := ' 0 '
RR_RSTR_E_S0  slbit := ' 0 '
RR_RSTR_E_S1  slbit := ' 0 '
RR_RSTW_S0  slbit := ' 0 '
RR_RSTW_S1  slbit := ' 0 '
NR_SIZER  slv ( a_range ) := ( others = > ' 0 ' )
NR_VAL  slbit := ' 0 '
NR_RSTR  slbit := ' 0 '
WADDR  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
RADDR  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
WADDR_BIN_W  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
RADDR_BIN_R  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
WADDR_BIN_R  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
RADDR_BIN_W  slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
GCW_RST  slbit := ' 0 '
GCW_CE  slbit := ' 0 '
GCR_RST  slbit := ' 0 '
GCR_CE  slbit := ' 0 '

Attributes

ASYNC_REG  string
ASYNC_REG  signal is " true "

Instantiations

ram  ram_1swar_1ar_gen <Entity ram_1swar_1ar_gen>
gcw  gray_cnt_gen <Entity gray_cnt_gen>
gcr  gray_cnt_gen <Entity gray_cnt_gen>
g2b_ww  gray2bin_gen <Entity gray2bin_gen>
g2b_wr  gray2bin_gen <Entity gray2bin_gen>
g2b_rr  gray2bin_gen <Entity gray2bin_gen>
g2b_rw  gray2bin_gen <Entity gray2bin_gen>

Detailed Description

Definition at line 55 of file fifo_2c_dram2.vhd.

Member Function/Procedure/Process Documentation

◆ proc_regw()

proc_regw (   CLKW)

Definition at line 167 of file fifo_2c_dram2.vhd.

◆ proc_nextw()

proc_nextw (   RW_BUSY ,
  RW_SIZEW ,
  RW_RSTW ,
  RW_RSTW_E_S1 ,
  RW_RSTR_S1 ,
  ENA ,
  RESETW ,
  RADDR_BIN_W ,
  WADDR_BIN_W  
)
Process

Definition at line 182 of file fifo_2c_dram2.vhd.

◆ proc_regr()

proc_regr (   CLKR  
)
Process

Definition at line 242 of file fifo_2c_dram2.vhd.

◆ proc_nextr()

proc_nextr (   RR_VAL ,
  RR_SIZER ,
  RR_RSTR ,
  RR_RSTR_E_S1 ,
  RR_RSTW_S1 ,
  HOLD ,
  RESETR ,
  RADDR_BIN_R ,
  WADDR_BIN_R  
)
Process

Definition at line 257 of file fifo_2c_dram2.vhd.

Member Data Documentation

◆ a_range

a_range integer range AWIDTH - 1 downto 0
Subtype

Definition at line 57 of file fifo_2c_dram2.vhd.

◆ RW_RADDR_S0

RW_RADDR_S0 slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 59 of file fifo_2c_dram2.vhd.

◆ RW_RADDR_S1

RW_RADDR_S1 slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 60 of file fifo_2c_dram2.vhd.

◆ RW_SIZEW

RW_SIZEW slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 61 of file fifo_2c_dram2.vhd.

◆ RW_BUSY

RW_BUSY slbit := ' 0 '
Signal

Definition at line 62 of file fifo_2c_dram2.vhd.

◆ RW_RSTW

RW_RSTW slbit := ' 0 '
Signal

Definition at line 63 of file fifo_2c_dram2.vhd.

◆ RW_RSTW_E_S0

RW_RSTW_E_S0 slbit := ' 0 '
Signal

Definition at line 64 of file fifo_2c_dram2.vhd.

◆ RW_RSTW_E_S1

RW_RSTW_E_S1 slbit := ' 0 '
Signal

Definition at line 65 of file fifo_2c_dram2.vhd.

◆ RW_RSTR_S0

RW_RSTR_S0 slbit := ' 0 '
Signal

Definition at line 66 of file fifo_2c_dram2.vhd.

◆ RW_RSTR_S1

RW_RSTR_S1 slbit := ' 0 '
Signal

Definition at line 67 of file fifo_2c_dram2.vhd.

◆ NW_SIZEW

NW_SIZEW slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 69 of file fifo_2c_dram2.vhd.

◆ NW_BUSY

NW_BUSY slbit := ' 0 '
Signal

Definition at line 70 of file fifo_2c_dram2.vhd.

◆ NW_RSTW

NW_RSTW slbit := ' 0 '
Signal

Definition at line 71 of file fifo_2c_dram2.vhd.

◆ RR_WADDR_S0

RR_WADDR_S0 slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 73 of file fifo_2c_dram2.vhd.

◆ RR_WADDR_S1

RR_WADDR_S1 slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 74 of file fifo_2c_dram2.vhd.

◆ RR_SIZER

RR_SIZER slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 75 of file fifo_2c_dram2.vhd.

◆ RR_VAL

RR_VAL slbit := ' 0 '
Signal

Definition at line 76 of file fifo_2c_dram2.vhd.

◆ RR_RSTR

RR_RSTR slbit := ' 0 '
Signal

Definition at line 77 of file fifo_2c_dram2.vhd.

◆ RR_RSTR_E_S0

RR_RSTR_E_S0 slbit := ' 0 '
Signal

Definition at line 78 of file fifo_2c_dram2.vhd.

◆ RR_RSTR_E_S1

RR_RSTR_E_S1 slbit := ' 0 '
Signal

Definition at line 79 of file fifo_2c_dram2.vhd.

◆ RR_RSTW_S0

RR_RSTW_S0 slbit := ' 0 '
Signal

Definition at line 80 of file fifo_2c_dram2.vhd.

◆ RR_RSTW_S1

RR_RSTW_S1 slbit := ' 0 '
Signal

Definition at line 81 of file fifo_2c_dram2.vhd.

◆ NR_SIZER

NR_SIZER slv ( a_range ) := ( others = > ' 0 ' )
Signal

Definition at line 83 of file fifo_2c_dram2.vhd.

◆ NR_VAL

NR_VAL slbit := ' 0 '
Signal

Definition at line 84 of file fifo_2c_dram2.vhd.

◆ NR_RSTR

NR_RSTR slbit := ' 0 '
Signal

Definition at line 85 of file fifo_2c_dram2.vhd.

◆ WADDR

WADDR slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 87 of file fifo_2c_dram2.vhd.

◆ RADDR

RADDR slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 88 of file fifo_2c_dram2.vhd.

◆ WADDR_BIN_W

WADDR_BIN_W slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 89 of file fifo_2c_dram2.vhd.

◆ RADDR_BIN_R

RADDR_BIN_R slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 90 of file fifo_2c_dram2.vhd.

◆ WADDR_BIN_R

WADDR_BIN_R slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 91 of file fifo_2c_dram2.vhd.

◆ RADDR_BIN_W

RADDR_BIN_W slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 92 of file fifo_2c_dram2.vhd.

◆ GCW_RST

GCW_RST slbit := ' 0 '
Signal

Definition at line 94 of file fifo_2c_dram2.vhd.

◆ GCW_CE

GCW_CE slbit := ' 0 '
Signal

Definition at line 95 of file fifo_2c_dram2.vhd.

◆ GCR_RST

GCR_RST slbit := ' 0 '
Signal

Definition at line 96 of file fifo_2c_dram2.vhd.

◆ GCR_CE

GCR_CE slbit := ' 0 '
Signal

Definition at line 97 of file fifo_2c_dram2.vhd.

◆ ASYNC_REG [1/2]

ASYNC_REG string
Attribute

Definition at line 99 of file fifo_2c_dram2.vhd.

◆ ASYNC_REG [2/2]

ASYNC_REG signal is " true "
Attribute

Definition at line 101 of file fifo_2c_dram2.vhd.

◆ ram

ram ram_1swar_1ar_gen
Instantiation

Definition at line 129 of file fifo_2c_dram2.vhd.

◆ gcw

gcw gray_cnt_gen
Instantiation

Definition at line 139 of file fifo_2c_dram2.vhd.

◆ gcr

gcr gray_cnt_gen
Instantiation

Definition at line 149 of file fifo_2c_dram2.vhd.

◆ g2b_ww

g2b_ww gray2bin_gen
Instantiation

Definition at line 153 of file fifo_2c_dram2.vhd.

◆ g2b_wr

g2b_wr gray2bin_gen
Instantiation

Definition at line 156 of file fifo_2c_dram2.vhd.

◆ g2b_rr

g2b_rr gray2bin_gen
Instantiation

Definition at line 159 of file fifo_2c_dram2.vhd.

◆ g2b_rw

g2b_rw gray2bin_gen
Instantiation

Definition at line 162 of file fifo_2c_dram2.vhd.

The documentation for this design unit was generated from the following file: