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W11 CPU core and support modules
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ram_2swsr_xfirst_gen_unisim.vhd
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1-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
7-- Description: Dual-Port RAM with with two synchronous read/write ports
8-- Direct instantiation of Xilinx UNISIM primitives
9--
10-- Dependencies: -
11-- Test bench: -
12-- Target Devices: Spartan-3, Virtex-2,-4
13-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
14-- Revision History:
15-- Date Rev Version Comment
16-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
17-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
18-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23
24library unisim;
25use unisim.vcomponents.ALL;
26
27use work.slvtypes.all;
28
29entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
30 generic (
31 AWIDTH : positive := 11; -- address port width
32 DWIDTH : positive := 9; -- data port width
33 WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
34 port(
35 CLKA : in slbit; -- clock port A
36 CLKB : in slbit; -- clock port B
37 ENA : in slbit; -- enable port A
38 ENB : in slbit; -- enable port B
39 WEA : in slbit; -- write enable port A
40 WEB : in slbit; -- write enable port B
41 ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
42 ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
43 DIA : in slv(DWIDTH-1 downto 0); -- data in port A
44 DIB : in slv(DWIDTH-1 downto 0); -- data in port B
45 DOA : out slv(DWIDTH-1 downto 0); -- data out port A
46 DOB : out slv(DWIDTH-1 downto 0) -- data out port B
47 );
48end ram_2swsr_xfirst_gen_unisim;
49
50
51architecture syn of ram_2swsr_xfirst_gen_unisim is
52
53 constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
54 ((DWIDTH+35)/36)=((DWIDTH+31)/32);
55 constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
56 ((DWIDTH+17)/18)=((DWIDTH+16)/16);
57 constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
58 ((DWIDTH+8)/9)=((DWIDTH+7)/8);
59
60begin
61
62 assert AWIDTH>=9 and AWIDTH<=14
63 report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
64 severity failure;
65
66 AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
67 constant dw_mem : positive := ((DWIDTH+35)/36)*36;
68 signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
69 signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
70 signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
71 signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
72 begin
73
74 DI_PAD: if dw_mem>DWIDTH generate
75 L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
76 L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
77 end generate DI_PAD;
78 L_DIA(DIA'range) <= DIA;
79 L_DIB(DIB'range) <= DIB;
80
81 GL: for i in dw_mem/36-1 downto 0 generate
82 MEM : RAMB16_S36_S36
83 generic map (
84 INIT_A => O"000000000000",
85 INIT_B => O"000000000000",
86 SRVAL_A => O"000000000000",
87 SRVAL_B => O"000000000000",
88 WRITE_MODE_A => WRITE_MODE,
89 WRITE_MODE_B => WRITE_MODE)
90 port map (
91 DOA => L_DOA(36*i+31 downto 36*i),
92 DOB => L_DOB(36*i+31 downto 36*i),
93 DOPA => L_DOA(36*i+35 downto 36*i+32),
94 DOPB => L_DOB(36*i+35 downto 36*i+32),
95 ADDRA => ADDRA,
96 ADDRB => ADDRB,
97 CLKA => CLKA,
98 CLKB => CLKB,
99 DIA => L_DIA(36*i+31 downto 36*i),
100 DIB => L_DIB(36*i+31 downto 36*i),
101 DIPA => L_DIA(36*i+35 downto 36*i+32),
102 DIPB => L_DIB(36*i+35 downto 36*i+32),
103 ENA => ENA,
104 ENB => ENB,
105 SSRA => '0',
106 SSRB => '0',
107 WEA => WEA,
108 WEB => WEB
109 );
110 end generate GL;
111
112 DOA <= L_DOA(DOA'range);
113 DOB <= L_DOB(DOB'range);
114
115 end generate AW_09_S36;
116
117 AW_09_S32: if AWIDTH=9 and ok_mod32 generate
118 GL: for i in DWIDTH/32-1 downto 0 generate
119 MEM : RAMB16_S36_S36
120 generic map (
121 INIT_A => X"00000000",
122 INIT_B => X"00000000",
123 SRVAL_A => X"00000000",
124 SRVAL_B => X"00000000",
125 WRITE_MODE_A => WRITE_MODE,
126 WRITE_MODE_B => WRITE_MODE)
127 port map (
128 DOA => DOA(32*i+31 downto 32*i),
129 DOB => DOB(32*i+31 downto 32*i),
130 DOPA => open,
131 DOPB => open,
132 ADDRA => ADDRA,
133 ADDRB => ADDRB,
134 CLKA => CLKA,
135 CLKB => CLKB,
136 DIA => DIA(32*i+31 downto 32*i),
137 DIB => DIB(32*i+31 downto 32*i),
138 DIPA => "0000",
139 DIPB => "0000",
140 ENA => ENA,
141 ENB => ENB,
142 SSRA => '0',
143 SSRB => '0',
144 WEA => WEA,
145 WEB => WEB
146 );
147 end generate GL;
148 end generate AW_09_S32;
149
150 AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
151 constant dw_mem : positive := ((DWIDTH+17)/18)*18;
152 signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
153 signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
154 signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
155 signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
156 begin
157
158 DI_PAD: if dw_mem>DWIDTH generate
159 L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
160 L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
161 end generate DI_PAD;
162 L_DIA(DIA'range) <= DIA;
163 L_DIB(DIB'range) <= DIB;
164
165 GL: for i in dw_mem/18-1 downto 0 generate
166 MEM : RAMB16_S18_S18
167 generic map (
168 INIT_A => O"000000",
169 INIT_B => O"000000",
170 SRVAL_A => O"000000",
171 SRVAL_B => O"000000",
172 WRITE_MODE_A => WRITE_MODE,
173 WRITE_MODE_B => WRITE_MODE)
174 port map (
175 DOA => L_DOA(18*i+15 downto 18*i),
176 DOB => L_DOB(18*i+15 downto 18*i),
177 DOPA => L_DOA(18*i+17 downto 18*i+16),
178 DOPB => L_DOB(18*i+17 downto 18*i+16),
179 ADDRA => ADDRA,
180 ADDRB => ADDRB,
181 CLKA => CLKA,
182 CLKB => CLKB,
183 DIA => L_DIA(18*i+15 downto 18*i),
184 DIB => L_DIB(18*i+15 downto 18*i),
185 DIPA => L_DIA(18*i+17 downto 18*i+16),
186 DIPB => L_DIB(18*i+17 downto 18*i+16),
187 ENA => ENA,
188 ENB => ENB,
189 SSRA => '0',
190 SSRB => '0',
191 WEA => WEA,
192 WEB => WEB
193 );
194 end generate GL;
195
196 DOA <= L_DOA(DOA'range);
197 DOB <= L_DOB(DOB'range);
198
199 end generate AW_10_S18;
200
201 AW_10_S16: if AWIDTH=10 and ok_mod16 generate
202 GL: for i in DWIDTH/16-1 downto 0 generate
203 MEM : RAMB16_S18_S18
204 generic map (
205 INIT_A => X"0000",
206 INIT_B => X"0000",
207 SRVAL_A => X"0000",
208 SRVAL_B => X"0000",
209 WRITE_MODE_A => WRITE_MODE,
210 WRITE_MODE_B => WRITE_MODE)
211 port map (
212 DOA => DOA(16*i+15 downto 16*i),
213 DOB => DOB(16*i+15 downto 16*i),
214 DOPA => open,
215 DOPB => open,
216 ADDRA => ADDRA,
217 ADDRB => ADDRB,
218 CLKA => CLKA,
219 CLKB => CLKB,
220 DIA => DIA(16*i+15 downto 16*i),
221 DIB => DIB(16*i+15 downto 16*i),
222 DIPA => "00",
223 DIPB => "00",
224 ENA => ENA,
225 ENB => ENB,
226 SSRA => '0',
227 SSRB => '0',
228 WEA => WEA,
229 WEB => WEB
230 );
231 end generate GL;
232 end generate AW_10_S16;
233
234 AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
235 constant dw_mem : positive := ((DWIDTH+8)/9)*9;
236 signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
237 signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
238 signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
239 signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
240 begin
241
242 DI_PAD: if dw_mem>DWIDTH generate
243 L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
244 L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
245 end generate DI_PAD;
246 L_DIA(DIA'range) <= DIA;
247 L_DIB(DIB'range) <= DIB;
248
249 GL: for i in dw_mem/9-1 downto 0 generate
250 MEM : RAMB16_S9_S9
251 generic map (
252 INIT_A => O"000",
253 INIT_B => O"000",
254 SRVAL_A => O"000",
255 SRVAL_B => O"000",
256 WRITE_MODE_A => WRITE_MODE,
257 WRITE_MODE_B => WRITE_MODE)
258 port map (
259 DOA => L_DOA(9*i+7 downto 9*i),
260 DOB => L_DOB(9*i+7 downto 9*i),
261 DOPA => L_DOA(9*i+8 downto 9*i+8),
262 DOPB => L_DOB(9*i+8 downto 9*i+8),
263 ADDRA => ADDRA,
264 ADDRB => ADDRB,
265 CLKA => CLKA,
266 CLKB => CLKB,
267 DIA => L_DIA(9*i+7 downto 9*i),
268 DIB => L_DIB(9*i+7 downto 9*i),
269 DIPA => L_DIA(9*i+8 downto 9*i+8),
270 DIPB => L_DIB(9*i+8 downto 9*i+8),
271 ENA => ENA,
272 ENB => ENB,
273 SSRA => '0',
274 SSRB => '0',
275 WEA => WEA,
276 WEB => WEB
277 );
278 end generate GL;
279
280 DOA <= L_DOA(DOA'range);
281 DOB <= L_DOB(DOB'range);
282
283 end generate AW_11_S9;
284
285 AW_11_S8: if AWIDTH=11 and ok_mod08 generate
286 GL: for i in DWIDTH/8-1 downto 0 generate
287 MEM : RAMB16_S9_S9
288 generic map (
289 INIT_A => X"00",
290 INIT_B => X"00",
291 SRVAL_A => X"00",
292 SRVAL_B => X"00",
293 WRITE_MODE_A => WRITE_MODE,
294 WRITE_MODE_B => WRITE_MODE)
295 port map (
296 DOA => DOA(8*i+7 downto 8*i),
297 DOB => DOB(8*i+7 downto 8*i),
298 DOPA => open,
299 DOPB => open,
300 ADDRA => ADDRA,
301 ADDRB => ADDRB,
302 CLKA => CLKA,
303 CLKB => CLKB,
304 DIA => DIA(8*i+7 downto 8*i),
305 DIB => DIB(8*i+7 downto 8*i),
306 DIPA => "0",
307 DIPB => "0",
308 ENA => ENA,
309 ENB => ENB,
310 SSRA => '0',
311 SSRB => '0',
312 WEA => WEA,
313 WEB => WEB
314 );
315 end generate GL;
316 end generate AW_11_S8;
317
318 AW_12_S4: if AWIDTH = 12 generate
319 constant dw_mem : positive := ((DWIDTH+3)/4)*4;
320 signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
321 signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
322 signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
323 signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
324 begin
325
326 DI_PAD: if dw_mem>DWIDTH generate
327 L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
328 L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
329 end generate DI_PAD;
330 L_DIA(DIA'range) <= DIA;
331 L_DIB(DIB'range) <= DIB;
332
333 GL: for i in dw_mem/4-1 downto 0 generate
334 MEM : RAMB16_S4_S4
335 generic map (
336 INIT_A => X"0",
337 INIT_B => X"0",
338 SRVAL_A => X"0",
339 SRVAL_B => X"0",
340 WRITE_MODE_A => WRITE_MODE,
341 WRITE_MODE_B => WRITE_MODE)
342 port map (
343 DOA => L_DOA(4*i+3 downto 4*i),
344 DOB => L_DOB(4*i+3 downto 4*i),
345 ADDRA => ADDRA,
346 ADDRB => ADDRB,
347 CLKA => CLKA,
348 CLKB => CLKB,
349 DIA => L_DIA(4*i+3 downto 4*i),
350 DIB => L_DIB(4*i+3 downto 4*i),
351 ENA => ENA,
352 ENB => ENB,
353 SSRA => '0',
354 SSRB => '0',
355 WEA => WEA,
356 WEB => WEB
357 );
358 end generate GL;
359
360 DOA <= L_DOA(DOA'range);
361 DOB <= L_DOB(DOB'range);
362
363 end generate AW_12_S4;
364
365 AW_13_S2: if AWIDTH = 13 generate
366 constant dw_mem : positive := ((DWIDTH+1)/2)*2;
367 signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
368 signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
369 signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
370 signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
371 begin
372
373 DI_PAD: if dw_mem>DWIDTH generate
374 L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
375 L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
376 end generate DI_PAD;
377 L_DIA(DIA'range) <= DIA;
378 L_DIB(DIB'range) <= DIB;
379
380 GL: for i in dw_mem/2-1 downto 0 generate
381 MEM : RAMB16_S2_S2
382 generic map (
383 INIT_A => "00",
384 INIT_B => "00",
385 SRVAL_A => "00",
386 SRVAL_B => "00",
387 WRITE_MODE_A => WRITE_MODE,
388 WRITE_MODE_B => WRITE_MODE)
389 port map (
390 DOA => L_DOA(2*i+1 downto 2*i),
391 DOB => L_DOB(2*i+1 downto 2*i),
392 ADDRA => ADDRA,
393 ADDRB => ADDRB,
394 CLKA => CLKA,
395 CLKB => CLKB,
396 DIA => L_DIA(2*i+1 downto 2*i),
397 DIB => L_DIB(2*i+1 downto 2*i),
398 ENA => ENA,
399 ENB => ENB,
400 SSRA => '0',
401 SSRB => '0',
402 WEA => WEA,
403 WEB => WEB
404 );
405 end generate GL;
406
407 DOA <= L_DOA(DOA'range);
408 DOB <= L_DOB(DOB'range);
409
410 end generate AW_13_S2;
411
412 AW_14_S1: if AWIDTH = 14 generate
413 GL: for i in DWIDTH-1 downto 0 generate
414 MEM : RAMB16_S1_S1
415 generic map (
416 INIT_A => "0",
417 INIT_B => "0",
418 SRVAL_A => "0",
419 SRVAL_B => "0",
420 WRITE_MODE_A => WRITE_MODE,
421 WRITE_MODE_B => WRITE_MODE)
422 port map (
423 DOA => DOA(i downto i),
424 DOB => DOB(i downto i),
425 ADDRA => ADDRA,
426 ADDRB => ADDRB,
427 CLKA => CLKA,
428 CLKB => CLKB,
429 DIA => DIA(i downto i),
430 DIB => DIB(i downto i),
431 ENA => ENA,
432 ENB => ENB,
433 SSRA => '0',
434 SSRB => '0',
435 WEA => WEA,
436 WEB => WEB
437 );
438 end generate GL;
439 end generate AW_14_S1;
440
441
442end syn;
443
444-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
445-- nonsense: INIT_A : bit_vector := X"000";
446-- This is a 12 bit value, while a 9 bit one is needed. Thus the
447-- explicit definition above.
ram_2swsr_xfirst_gen_unisim.syn
Definition: ram_2swsr_xfirst_gen_unisim.vhd:51
ram_2swsr_xfirst_gen_unisim.syn.dw_mem
positive :=(( DWIDTH+ 35)/ 36)* 36 dw_mem
Definition: ram_2swsr_xfirst_gen_unisim.vhd:67
ram_2swsr_xfirst_gen_unisim.syn.ok_mod16
boolean :=( DWIDTHmod 16)= 0and(( DWIDTH+ 17)/ 18)=(( DWIDTH+ 16)/ 16) ok_mod16
Definition: ram_2swsr_xfirst_gen_unisim.vhd:55
ram_2swsr_xfirst_gen_unisim.syn.ok_mod08
boolean :=( DWIDTHmod 32)= 0and(( DWIDTH+ 8)/ 9)=(( DWIDTH+ 7)/ 8) ok_mod08
Definition: ram_2swsr_xfirst_gen_unisim.vhd:57
ram_2swsr_xfirst_gen_unisim.syn.ok_mod32
boolean :=( DWIDTHmod 32)= 0and(( DWIDTH+ 35)/ 36)=(( DWIDTH+ 31)/ 32) ok_mod32
Definition: ram_2swsr_xfirst_gen_unisim.vhd:53
ram_2swsr_xfirst_gen_unisim.syn.L_DIB
slv( dw_mem- 1 downto 0) :=( others => '0') L_DIB
Definition: ram_2swsr_xfirst_gen_unisim.vhd:71
ram_2swsr_xfirst_gen_unisim.syn.L_DOA
slv( dw_mem- 1 downto 0) :=( others => '0') L_DOA
Definition: ram_2swsr_xfirst_gen_unisim.vhd:68
ram_2swsr_xfirst_gen_unisim.syn.L_DIA
slv( dw_mem- 1 downto 0) :=( others => '0') L_DIA
Definition: ram_2swsr_xfirst_gen_unisim.vhd:70
ram_2swsr_xfirst_gen_unisim.syn.L_DOB
slv( dw_mem- 1 downto 0) :=( others => '0') L_DOB
Definition: ram_2swsr_xfirst_gen_unisim.vhd:69
ram_2swsr_xfirst_gen_unisim
Definition: ram_2swsr_xfirst_gen_unisim.vhd:29
ram_2swsr_xfirst_gen_unisim.WEA
in WEA slbit
Definition: ram_2swsr_xfirst_gen_unisim.vhd:39
ram_2swsr_xfirst_gen_unisim.ENA
in ENA slbit
Definition: ram_2swsr_xfirst_gen_unisim.vhd:37
ram_2swsr_xfirst_gen_unisim.DIA
in DIA slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_xfirst_gen_unisim.vhd:43
ram_2swsr_xfirst_gen_unisim.AWIDTH
AWIDTH positive := 11
Definition: ram_2swsr_xfirst_gen_unisim.vhd:31
ram_2swsr_xfirst_gen_unisim.ENB
in ENB slbit
Definition: ram_2swsr_xfirst_gen_unisim.vhd:38
ram_2swsr_xfirst_gen_unisim.ADDRB
in ADDRB slv( AWIDTH- 1 downto 0)
Definition: ram_2swsr_xfirst_gen_unisim.vhd:42
ram_2swsr_xfirst_gen_unisim.CLKA
in CLKA slbit
Definition: ram_2swsr_xfirst_gen_unisim.vhd:35
ram_2swsr_xfirst_gen_unisim.WRITE_MODE
WRITE_MODE string := "READ_FIRST"
Definition: ram_2swsr_xfirst_gen_unisim.vhd:33
ram_2swsr_xfirst_gen_unisim.ADDRA
in ADDRA slv( AWIDTH- 1 downto 0)
Definition: ram_2swsr_xfirst_gen_unisim.vhd:41
ram_2swsr_xfirst_gen_unisim.CLKB
in CLKB slbit
Definition: ram_2swsr_xfirst_gen_unisim.vhd:36
ram_2swsr_xfirst_gen_unisim.DOB
out DOB slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_xfirst_gen_unisim.vhd:47
ram_2swsr_xfirst_gen_unisim.DWIDTH
DWIDTH positive := 9
Definition: ram_2swsr_xfirst_gen_unisim.vhd:32
ram_2swsr_xfirst_gen_unisim.DIB
in DIB slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_xfirst_gen_unisim.vhd:44
ram_2swsr_xfirst_gen_unisim.DOA
out DOA slv( DWIDTH- 1 downto 0)
Definition: ram_2swsr_xfirst_gen_unisim.vhd:45
ram_2swsr_xfirst_gen_unisim.WEB
in WEB slbit
Definition: ram_2swsr_xfirst_gen_unisim.vhd:40
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30
slvtypes.slv
std_logic_vector slv
Definition: slvtypes.vhd:31