w11 - vhd 0.794
W11 CPU core and support modules
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ram_2swsr_wfirst_gen_unisim.vhd
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1-- $Id: ram_2swsr_wfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: ram_2swsr_wfirst_gen - syn
7-- Description: Dual-Port RAM with with two synchronous read/write ports
8-- and 'read-through' semantics (as block RAM).
9-- Direct instantiation of Xilinx UNISIM primitives
10--
11-- Dependencies: -
12-- Test bench: -
13-- Target Devices: Spartan-3, Virtex-2,-4
14-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
15-- Revision History:
16-- Date Rev Version Comment
17-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
18-- 2008-03-02 122 1.0 Initial version
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23
24library unisim;
25use unisim.vcomponents.ALL;
26
27use work.slvtypes.all;
28use work.memlib.all;
29
30entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
31 generic (
32 AWIDTH : positive := 11; -- address port width
33 DWIDTH : positive := 9); -- data port width
34 port(
35 CLKA : in slbit; -- clock port A
36 CLKB : in slbit; -- clock port B
37 ENA : in slbit; -- enable port A
38 ENB : in slbit; -- enable port B
39 WEA : in slbit; -- write enable port A
40 WEB : in slbit; -- write enable port B
41 ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
42 ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
43 DIA : in slv(DWIDTH-1 downto 0); -- data in port A
44 DIB : in slv(DWIDTH-1 downto 0); -- data in port B
45 DOA : out slv(DWIDTH-1 downto 0); -- data out port A
46 DOB : out slv(DWIDTH-1 downto 0) -- data out port B
47 );
49
50
51architecture syn of ram_2swsr_wfirst_gen is
52begin
53
55 generic map (
56 AWIDTH => AWIDTH,
57 DWIDTH => DWIDTH,
58 WRITE_MODE => "WRITE_FIRST")
59 port map (
60 CLKA => CLKA,
61 CLKB => CLKB,
62 ENA => ENA,
63 ENB => ENB,
64 WEA => WEA,
65 WEB => WEB,
66 ADDRA => ADDRA,
67 ADDRB => ADDRB,
68 DIA => DIA,
69 DIB => DIB,
70 DOA => DOA,
71 DOB => DOB
72 );
73
74end syn;
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31