w11 - vhd 0.794
W11 CPU core and support modules
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miglib_arty.vhd
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1-- $Id: miglib_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: miglib_arty
7-- Description: MIG interface components - for arty
8--
9-- Dependencies: -
10-- Tool versions: viv 2017.2; ghdl 0.34
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2018-11-17 1071 1.0 Initial version
15------------------------------------------------------------------------------
16
17library ieee;
18use ieee.std_logic_1164.all;
19
20use work.slvtypes.all;
21use work.miglib.all;
22
23package miglib_arty is
24
25constant mig_bawidth : positive := 4; -- byte addr width
26constant mig_mawidth : positive := 28; -- mem addr width
27constant mig_mwidth : positive := 2**mig_bawidth; -- mask width ( 16)
28constant mig_dwidth : positive := 8*mig_mwidth; -- data width (128)
29
30component sramif_mig_arty is -- SRAM to DDR via MIG for arty
31 port (
32 CLK : in slbit; -- clock
33 RESET : in slbit; -- reset
34 REQ : in slbit; -- request
35 WE : in slbit; -- write enable
36 BUSY : out slbit; -- controller busy
37 ACK_R : out slbit; -- acknowledge read
38 ACK_W : out slbit; -- acknowledge write
39 ACT_R : out slbit; -- signal active read
40 ACT_W : out slbit; -- signal active write
41 ADDR : in slv20; -- address (32 bit word address)
42 BE : in slv4; -- byte enable
43 DI : in slv32; -- data in (memory view)
44 DO : out slv32; -- data out (memory view)
45 CLKMIG : in slbit; -- sys clock for mig core
46 CLKREF : in slbit; -- ref clock for mig core
47 TEMP : in slv12; -- die temperature
48 MONI : out sramif2migui_moni_type;-- monitor signals
49 DDR3_DQ : inout slv16; -- dram: data in/out
50 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
51 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
52 DDR3_ADDR : out slv14; -- dram: address
53 DDR3_BA : out slv3; -- dram: bank address
54 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
55 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
56 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
57 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
58 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
59 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
60 DDR3_CKE : out slv1; -- dram: clock enable
61 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
62 DDR3_DM : out slv2; -- dram: data input mask
63 DDR3_ODT : out slv1 -- dram: on-die termination
64 );
65end component;
66
67component migui_arty is -- MIG generated for arty
68 port (
69 DDR3_DQ : inout slv16; -- dram: data in/out
70 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
71 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
72 DDR3_ADDR : out slv14; -- dram: address
73 DDR3_BA : out slv3; -- dram: bank address
74 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
75 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
76 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
77 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
78 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
79 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
80 DDR3_CKE : out slv1; -- dram: clock enable
81 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
82 DDR3_DM : out slv2; -- dram: data input mask
83 DDR3_ODT : out slv1; -- dram: on-die termination
84 APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
85 APP_CMD : in slv3; -- MIGUI command
86 APP_EN : in slbit; -- MIGUI command enable
87 APP_WDF_DATA : in slv(mig_dwidth-1 downto 0); -- MIGUI write data
88 APP_WDF_END : in slbit; -- MIGUI write end
89 APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
90 APP_WDF_WREN : in slbit; -- MIGUI write enable
91 APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
92 APP_RD_DATA_END : out slbit; -- MIGUI read end
93 APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
94 APP_RDY : out slbit; -- MIGUI ready for cmd
95 APP_WDF_RDY : out slbit; -- MIGUI ready for data write
96 APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
97 APP_REF_REQ : in slbit; -- MIGUI refresh reques
98 APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
99 APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
100 APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
101 APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
102 UI_CLK : out slbit; -- MIGUI clock
103 UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
104 INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
105 SYS_CLK_I : in slbit; -- MIGUI system clock
106 CLK_REF_I : in slbit; -- MIGUI reference clock
107 DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
108 SYS_RST : in slbit -- MIGUI system reset
109 );
110end component;
111
112end package miglib_arty;
positive := 28 mig_mawidth
Definition: miglib_arty.vhd:26
positive := 2** mig_bawidth mig_mwidth
Definition: miglib_arty.vhd:27
positive := 4 mig_bawidth
Definition: miglib_arty.vhd:25
positive := 8* mig_mwidth mig_dwidth
Definition: miglib_arty.vhd:28
out UI_CLK slbit
out DDR3_CK_P slv1
out APP_RD_DATA slv( mig_dwidth- 1 downto 0)
out APP_RDY slbit
out APP_RD_DATA_VALID slbit
out DDR3_DM slv2
out APP_REF_ACK slbit
out APP_RD_DATA_END slbit
out DDR3_RESET_N slbit
out DDR3_BA slv3
inout DDR3_DQ slv16
in APP_WDF_MASK slv( mig_mwidth- 1 downto 0)
in APP_WDF_END slbit
in DEVICE_TEMP_I slv12
out INIT_CALIB_COMPLETE slbit
in APP_SR_REQ slbit
out DDR3_WE_N slbit
out DDR3_CKE slv1
out DDR3_ADDR slv14
out DDR3_ODT slv1
out DDR3_CAS_N slbit
out DDR3_CK_N slv1
inout DDR3_DQS_P slv2
in APP_REF_REQ slbit
in SYS_RST slbit
out APP_ZQ_ACK slbit
out APP_WDF_RDY slbit
inout DDR3_DQS_N slv2
in APP_ZQ_REQ slbit
in CLK_REF_I slbit
in APP_WDF_WREN slbit
out APP_SR_ACTIVE slbit
in APP_EN slbit
in APP_CMD slv3
in APP_ADDR slv( mig_mawidth- 1 downto 0)
in SYS_CLK_I slbit
out DDR3_RAS_N slbit
out DDR3_CS_N slv1
in APP_WDF_DATA slv( mig_dwidth- 1 downto 0)
out UI_CLK_SYNC_RST slbit
std_logic_vector( 13 downto 0) slv14
Definition: slvtypes.vhd:46
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
out DDR3_RESET_N slbit
inout DDR3_DQ slv16
out DDR3_WE_N slbit
out DDR3_ADDR slv14
out DDR3_CAS_N slbit
inout DDR3_DQS_P slv2
out MONI sramif2migui_moni_type
inout DDR3_DQS_N slv2
out DDR3_RAS_N slbit