w11 - vhd 0.794
W11 CPU core and support modules
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gray_cnt_4.vhd
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1-- $Id: gray_cnt_4.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007--2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: gray_cnt_4 - syn
7-- Description: 4 bit Gray code counter (ROM based)
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
13-- Revision History:
14-- Date Rev Version Comment
15-- 2017-01-07 840 1.1 disable fsm recognition in vivado
16-- 2007-12-26 106 1.0 Initial version
17--
18-- Some synthesis results:
19-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
20-- LUT Flop clock(xst est.)
21-- 4 4 365MHz/ 2.76ns
22------------------------------------------------------------------------------
23
24library ieee;
25use ieee.std_logic_1164.all;
26
27use work.slvtypes.all;
28
29entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
30 port (
31 CLK : in slbit; -- clock
32 RESET : in slbit := '0'; -- reset
33 CE : in slbit := '1'; -- count enable
34 DATA : out slv4 -- data out
35 );
36end entity gray_cnt_4;
37
38
39architecture syn of gray_cnt_4 is
40
41 signal R_DATA : slv4 := (others=>'0');
42 signal N_DATA : slv4 := (others=>'0');
43
44 -- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
45 -- inferred. For 4 bit the coding was 'Gray', but see remarks in
46 -- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
47
48 attribute fsm_extract : string;
49 attribute fsm_extract of R_DATA : signal is "no";
50 attribute rom_style : string;
51 attribute rom_style of N_DATA : signal is "distributed";
52
53 -- Note: vivado started with -fsm_extraction one_hot didn't fsm recognize
54 -- this code up to 2016.2. With 2016.3 and later it is converted into a
55 -- 31 state one-hot fsm, unless explicitely suppressed
56 attribute fsm_encoding : string;
57 attribute fsm_encoding of R_DATA : signal is "none";
58
59begin
60
61 proc_regs: process (CLK)
62 begin
63
64 if rising_edge(CLK) then
65 if RESET = '1' then
66 R_DATA <= (others=>'0');
67 elsif CE = '1' then
68 R_DATA <= N_DATA;
69 end if;
70 end if;
71 end process proc_regs;
72
73 proc_next: process (R_DATA)
74 begin
75
76 N_DATA <= (others=>'0');
77 case R_DATA is
78 when "0000" => N_DATA <= "0001"; -- 0
79 when "0001" => N_DATA <= "0011"; -- 1
80 when "0011" => N_DATA <= "0010"; -- 2
81 when "0010" => N_DATA <= "0110"; -- 3
82 when "0110" => N_DATA <= "0111"; -- 4
83 when "0111" => N_DATA <= "0101"; -- 5
84 when "0101" => N_DATA <= "0100"; -- 6
85 when "0100" => N_DATA <= "1100"; -- 7
86 when "1100" => N_DATA <= "1101"; -- 8
87 when "1101" => N_DATA <= "1111"; -- 9
88 when "1111" => N_DATA <= "1110"; -- 10
89 when "1110" => N_DATA <= "1010"; -- 11
90 when "1010" => N_DATA <= "1011"; -- 12
91 when "1011" => N_DATA <= "1001"; -- 13
92 when "1001" => N_DATA <= "1000"; -- 14
93 when "1000" => N_DATA <= "0000"; -- 15
94 when others => null;
95 end case;
96 end process proc_next;
97
98 DATA <= R_DATA;
99
100end syn;
101
string rom_style
Definition: gray_cnt_4.vhd:50
slv4 :=( others => '0') R_DATA
Definition: gray_cnt_4.vhd:41
slv4 :=( others => '0') N_DATA
Definition: gray_cnt_4.vhd:42
string fsm_encoding
Definition: gray_cnt_4.vhd:56
string fsm_extract
Definition: gray_cnt_4.vhd:48
in CE slbit := '1'
Definition: gray_cnt_4.vhd:33
out DATA slv4
Definition: gray_cnt_4.vhd:35
in CLK slbit
Definition: gray_cnt_4.vhd:31
in RESET slbit := '0'
Definition: gray_cnt_4.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic slbit
Definition: slvtypes.vhd:30