w11 - vhd 0.794
W11 CPU core and support modules
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Components | Constants | Instantiations | Processes | Signals
syn Architecture Reference
Architecture >> syn

Processes

proc_moni 

Components

tbu_rlink_sp1c  <Entity tbu_rlink_sp1c>

Constants

CDWIDTH  positive := 13
c_cdinit  natural := 0

Signals

RRI_RXSD  slbit := ' 0 '
RRI_TXSD  slbit := ' 0 '
RTS_N  slbit := ' 0 '
RXDATA  slv8 := ( others = > ' 0 ' )
RXVAL  slbit := ' 0 '
RXACT  slbit := ' 0 '
TXDATA  slv8 := ( others = > ' 0 ' )
TXENA  slbit := ' 0 '
TXBUSY  slbit := ' 0 '
CLKDIV  slv13 := slv ( to_unsigned ( c_cdinit , CDWIDTH ) )
CLK_CYCLE  integer := 0

Instantiations

tbu  tbu_rlink_sp1c <Entity tbu_rlink_sp1c>
uartrx  serport_uart_rx <Entity serport_uart_rx>
uarttx  serport_uart_tx <Entity serport_uart_tx>
b2cd  byte2cdata <Entity byte2cdata>
cd2b  cdata2byte <Entity cdata2byte>
clkcnt  simclkcnt <Entity simclkcnt>

Detailed Description

Definition at line 92 of file tbd_rlink_sp1c.vhd.

Member Function/Procedure/Process Documentation

◆ proc_moni()

proc_moni

Definition at line 220 of file tbd_rlink_sp1c.vhd.

Member Data Documentation

◆ CDWIDTH

CDWIDTH positive := 13
Constant

Definition at line 94 of file tbd_rlink_sp1c.vhd.

◆ c_cdinit

c_cdinit natural := 0
Constant

Definition at line 95 of file tbd_rlink_sp1c.vhd.

◆ RRI_RXSD

RRI_RXSD slbit := ' 0 '
Signal

Definition at line 97 of file tbd_rlink_sp1c.vhd.

◆ RRI_TXSD

RRI_TXSD slbit := ' 0 '
Signal

Definition at line 98 of file tbd_rlink_sp1c.vhd.

◆ RTS_N

RTS_N slbit := ' 0 '
Signal

Definition at line 99 of file tbd_rlink_sp1c.vhd.

◆ RXDATA

RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 100 of file tbd_rlink_sp1c.vhd.

◆ RXVAL

RXVAL slbit := ' 0 '
Signal

Definition at line 101 of file tbd_rlink_sp1c.vhd.

◆ RXACT

RXACT slbit := ' 0 '
Signal

Definition at line 102 of file tbd_rlink_sp1c.vhd.

◆ TXDATA

TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 103 of file tbd_rlink_sp1c.vhd.

◆ TXENA

TXENA slbit := ' 0 '
Signal

Definition at line 104 of file tbd_rlink_sp1c.vhd.

◆ TXBUSY

TXBUSY slbit := ' 0 '
Signal

Definition at line 105 of file tbd_rlink_sp1c.vhd.

◆ CLKDIV

CLKDIV slv13 := slv ( to_unsigned ( c_cdinit , CDWIDTH ) )
Signal

Definition at line 106 of file tbd_rlink_sp1c.vhd.

◆ CLK_CYCLE

CLK_CYCLE integer := 0
Signal

Definition at line 107 of file tbd_rlink_sp1c.vhd.

◆ tbu_rlink_sp1c

tbu_rlink_sp1c
Component

Definition at line 109 of file tbd_rlink_sp1c.vhd.

◆ tbu

tbu tbu_rlink_sp1c
Instantiation

Definition at line 160 of file tbd_rlink_sp1c.vhd.

◆ uartrx

uartrx serport_uart_rx
Instantiation

Definition at line 174 of file tbd_rlink_sp1c.vhd.

◆ uarttx

uarttx serport_uart_tx
Instantiation

Definition at line 187 of file tbd_rlink_sp1c.vhd.

◆ b2cd

b2cd byte2cdata
Instantiation

Definition at line 202 of file tbd_rlink_sp1c.vhd.

◆ cd2b

cd2b cdata2byte
Instantiation

Definition at line 216 of file tbd_rlink_sp1c.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 218 of file tbd_rlink_sp1c.vhd.

The documentation for this design unit was generated from the following file: