sim Architecture Reference

Architecture >> sim

Processes
proc_conf
proc_stim

Signals
CLK_CYCLE	integer := 0
CEXT_CYCLE	slv32 := ( others = > ' 0 ' )
CEXT_RXDATA	slv32 := ( others = > ' 0 ' )
CEXT_RXVAL	slbit := ' 0 '
CEXT_RXHOLD	slbit := ' 1 '
CONF_DONE	slbit := ' 0 '

Instantiations
clkcnt	simclkcnt <Entity simclkcnt>
cext_iface	rlink_cext_iface <Entity rlink_cext_iface>

Detailed Description

Definition at line 58 of file tbcore_rlink.vhd.

Member Function/Procedure/Process Documentation

proc_conf()

proc_conf

Definition at line 84 of file tbcore_rlink.vhd.

proc_stim()

proc_stim ( )

Process

Definition at line 186 of file tbcore_rlink.vhd.

Member Data Documentation

CLK_CYCLE

CLK_CYCLE integer := 0

Signal

Definition at line 60 of file tbcore_rlink.vhd.

CEXT_CYCLE

CEXT_CYCLE slv32 := ( others = > ' 0 ' )

Signal

Definition at line 61 of file tbcore_rlink.vhd.

CEXT_RXDATA

CEXT_RXDATA slv32 := ( others = > ' 0 ' )

Signal

Definition at line 62 of file tbcore_rlink.vhd.

CEXT_RXVAL

CEXT_RXVAL slbit := ' 0 '

Signal

Definition at line 63 of file tbcore_rlink.vhd.

CEXT_RXHOLD

CEXT_RXHOLD slbit := ' 1 '

Signal

Definition at line 64 of file tbcore_rlink.vhd.

CONF_DONE

CONF_DONE slbit := ' 0 '

Signal

Definition at line 65 of file tbcore_rlink.vhd.

clkcnt

clkcnt simclkcnt

Instantiation

Definition at line 69 of file tbcore_rlink.vhd.

cext_iface

cext_iface rlink_cext_iface

Instantiation

Definition at line 80 of file tbcore_rlink.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/rlink/tbcore/tbcore_rlink.vhd