w11 - vhd 0.794
W11 CPU core and support modules
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Instantiations | Procedures | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_port_mux  ( ACTPORT , BREAK , UART_TXD , CTS_N , P0_TXD , P0_RTS_N , P1_TXD , P1_RTS_N )
proc_cts  ( CLKS )
proc_xonrxok  ( CLKS )
proc_xontxok  ( CLKS )
proc_stim 
proc_moni 

Procedures

  waitclk( ncyc: in integer )

Signals

CLK_CYCLE  integer := 0
UART_RESET  slbit := ' 0 '
UART_RXD  slbit := ' 1 '
UART_TXD  slbit := ' 1 '
CTS_N  slbit := ' 0 '
RTS_N  slbit := ' 0 '
CLKDIV  slv13 := ( others = > ' 0 ' )
RXDATA  slv8 := ( others = > ' 0 ' )
RXVAL  slbit := ' 0 '
RXERR  slbit := ' 0 '
RXACT  slbit := ' 0 '
TXDATA  slv8 := ( others = > ' 0 ' )
TXENA  slbit := ' 0 '
TXBUSY  slbit := ' 0 '
UART_TXDATA  slv8 := ( others = > ' 0 ' )
UART_TXENA  slbit := ' 0 '
UART_TXBUSY  slbit := ' 0 '
ACTPORT  slbit := ' 0 '
BREAK  slbit := ' 0 '
CTS_CYCLE  integer := 0
CTS_FRACT  integer := 0
XON_CYCLE  integer := 0
XON_FRACT  integer := 0
S2M_ACTIVE  slbit := ' 0 '
S2M_SIZE  integer := 0
S2M_ENAESC  slbit := ' 0 '
S2M_ENAXON  slbit := ' 0 '
M2S_XONSEEN  slbit := ' 0 '
M2S_XOFFSEEN  slbit := ' 0 '
R_XONRXOK  slbit := ' 1 '
R_XONTXOK  slbit := ' 1 '

Instantiations

clkcnt  simclkcnt <Entity simclkcnt>
uart  serport_uart_rxtx_tb <Entity serport_uart_rxtx_tb>
xontx  serport_xontx_tb <Entity serport_xontx_tb>

Detailed Description

Definition at line 56 of file tb_tst_serloop.vhd.

Member Function/Procedure/Process Documentation

◆ proc_port_mux()

proc_port_mux (   ACTPORT,
  BREAK,
  UART_TXD,
  CTS_N,
  P0_TXD,
  P0_RTS_N,
  P1_TXD,
  P1_RTS_N 
)

Definition at line 136 of file tb_tst_serloop.vhd.

◆ proc_cts()

proc_cts (   CLKS  
)
Process

Definition at line 164 of file tb_tst_serloop.vhd.

◆ proc_xonrxok()

proc_xonrxok (   CLKS  
)
Process

Definition at line 191 of file tb_tst_serloop.vhd.

◆ proc_xontxok()

proc_xontxok (   CLKS  
)
Process

Definition at line 216 of file tb_tst_serloop.vhd.

◆ waitclk()

waitclk (   ncyc in integer  
)
Procedure

Definition at line 245 of file tb_tst_serloop.vhd.

◆ proc_stim()

proc_stim ( )
Process

◆ proc_moni()

proc_moni ( )
Process

Definition at line 449 of file tb_tst_serloop.vhd.

Member Data Documentation

◆ CLK_CYCLE

CLK_CYCLE integer := 0
Signal

Definition at line 58 of file tb_tst_serloop.vhd.

◆ UART_RESET

UART_RESET slbit := ' 0 '
Signal

Definition at line 60 of file tb_tst_serloop.vhd.

◆ UART_RXD

UART_RXD slbit := ' 1 '
Signal

Definition at line 61 of file tb_tst_serloop.vhd.

◆ UART_TXD

UART_TXD slbit := ' 1 '
Signal

Definition at line 62 of file tb_tst_serloop.vhd.

◆ CTS_N

CTS_N slbit := ' 0 '
Signal

Definition at line 63 of file tb_tst_serloop.vhd.

◆ RTS_N

RTS_N slbit := ' 0 '
Signal

Definition at line 64 of file tb_tst_serloop.vhd.

◆ CLKDIV

CLKDIV slv13 := ( others = > ' 0 ' )
Signal

Definition at line 66 of file tb_tst_serloop.vhd.

◆ RXDATA

RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 67 of file tb_tst_serloop.vhd.

◆ RXVAL

RXVAL slbit := ' 0 '
Signal

Definition at line 68 of file tb_tst_serloop.vhd.

◆ RXERR

RXERR slbit := ' 0 '
Signal

Definition at line 69 of file tb_tst_serloop.vhd.

◆ RXACT

RXACT slbit := ' 0 '
Signal

Definition at line 70 of file tb_tst_serloop.vhd.

◆ TXDATA

TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 71 of file tb_tst_serloop.vhd.

◆ TXENA

TXENA slbit := ' 0 '
Signal

Definition at line 72 of file tb_tst_serloop.vhd.

◆ TXBUSY

TXBUSY slbit := ' 0 '
Signal

Definition at line 73 of file tb_tst_serloop.vhd.

◆ UART_TXDATA

UART_TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 75 of file tb_tst_serloop.vhd.

◆ UART_TXENA

UART_TXENA slbit := ' 0 '
Signal

Definition at line 76 of file tb_tst_serloop.vhd.

◆ UART_TXBUSY

UART_TXBUSY slbit := ' 0 '
Signal

Definition at line 77 of file tb_tst_serloop.vhd.

◆ ACTPORT

ACTPORT slbit := ' 0 '
Signal

Definition at line 79 of file tb_tst_serloop.vhd.

◆ BREAK

BREAK slbit := ' 0 '
Signal

Definition at line 80 of file tb_tst_serloop.vhd.

◆ CTS_CYCLE

CTS_CYCLE integer := 0
Signal

Definition at line 82 of file tb_tst_serloop.vhd.

◆ CTS_FRACT

CTS_FRACT integer := 0
Signal

Definition at line 83 of file tb_tst_serloop.vhd.

◆ XON_CYCLE

XON_CYCLE integer := 0
Signal

Definition at line 84 of file tb_tst_serloop.vhd.

◆ XON_FRACT

XON_FRACT integer := 0
Signal

Definition at line 85 of file tb_tst_serloop.vhd.

◆ S2M_ACTIVE

S2M_ACTIVE slbit := ' 0 '
Signal

Definition at line 87 of file tb_tst_serloop.vhd.

◆ S2M_SIZE

S2M_SIZE integer := 0
Signal

Definition at line 88 of file tb_tst_serloop.vhd.

◆ S2M_ENAESC

S2M_ENAESC slbit := ' 0 '
Signal

Definition at line 89 of file tb_tst_serloop.vhd.

◆ S2M_ENAXON

S2M_ENAXON slbit := ' 0 '
Signal

Definition at line 90 of file tb_tst_serloop.vhd.

◆ M2S_XONSEEN

M2S_XONSEEN slbit := ' 0 '
Signal

Definition at line 92 of file tb_tst_serloop.vhd.

◆ M2S_XOFFSEEN

M2S_XOFFSEEN slbit := ' 0 '
Signal

Definition at line 93 of file tb_tst_serloop.vhd.

◆ R_XONRXOK

R_XONRXOK slbit := ' 1 '
Signal

Definition at line 95 of file tb_tst_serloop.vhd.

◆ R_XONTXOK

R_XONTXOK slbit := ' 1 '
Signal

Definition at line 96 of file tb_tst_serloop.vhd.

◆ clkcnt

clkcnt simclkcnt
Instantiation

Definition at line 100 of file tb_tst_serloop.vhd.

◆ uart

uart serport_uart_rxtx_tb
Instantiation

Definition at line 118 of file tb_tst_serloop.vhd.

◆ xontx

xontx serport_xontx_tb
Instantiation

Definition at line 134 of file tb_tst_serloop.vhd.

The documentation for this design unit was generated from the following file: