sim Architecture Reference

Architecture >> sim

Constants
clock_period	Delay_length := 10 ns
clock_offset	Delay_length := 200 ns
delay_time	Delay_length := 2 ns

Signals
CLK100	slbit := ' 0 '
CLKS	slbit := ' 0 '
CLKH	slbit := ' 0 '
I_RXD	slbit := ' 1 '
O_TXD	slbit := ' 1 '
I_SWI	slv16 := ( others = > ' 0 ' )
I_BTN	slv5 := ( others = > ' 0 ' )
RXD	slbit := ' 1 '
TXD	slbit := ' 1 '
SWI	slv16 := ( others = > ' 0 ' )
BTN	slv5 := ( others = > ' 0 ' )

Instantiations
sysclk	simclk <Entity simclk>
gen_clksys	sfs_gsim_core <Entity sfs_gsim_core>
gen_clkser	sfs_gsim_core <Entity sfs_gsim_core>
uut	sys_tst_serloop2_b3 <Entity sys_tst_serloop2_b3>
gentb	tb_tst_serloop <Entity tb_tst_serloop>

Detailed Description

Definition at line 37 of file tb_tst_serloop2_b3.vhd.

Member Data Documentation

CLK100

CLK100 slbit := ' 0 '

Signal

Definition at line 39 of file tb_tst_serloop2_b3.vhd.

CLKS

CLKS slbit := ' 0 '

Signal

Definition at line 41 of file tb_tst_serloop2_b3.vhd.

CLKH

CLKH slbit := ' 0 '

Signal

Definition at line 42 of file tb_tst_serloop2_b3.vhd.

I_RXD

I_RXD slbit := ' 1 '

Signal

Definition at line 44 of file tb_tst_serloop2_b3.vhd.

O_TXD

O_TXD slbit := ' 1 '

Signal

Definition at line 45 of file tb_tst_serloop2_b3.vhd.

I_SWI

I_SWI slv16 := ( others = > ' 0 ' )

Signal

Definition at line 46 of file tb_tst_serloop2_b3.vhd.

I_BTN

I_BTN slv5 := ( others = > ' 0 ' )

Signal

Definition at line 47 of file tb_tst_serloop2_b3.vhd.

RXD

RXD slbit := ' 1 '

Signal

Definition at line 49 of file tb_tst_serloop2_b3.vhd.

TXD

TXD slbit := ' 1 '

Signal

Definition at line 50 of file tb_tst_serloop2_b3.vhd.

SWI

SWI slv16 := ( others = > ' 0 ' )

Signal

Definition at line 51 of file tb_tst_serloop2_b3.vhd.

BTN

BTN slv5 := ( others = > ' 0 ' )

Signal

Definition at line 52 of file tb_tst_serloop2_b3.vhd.

clock_period

clock_period Delay_length := 10 ns

Constant

Definition at line 54 of file tb_tst_serloop2_b3.vhd.

clock_offset

clock_offset Delay_length := 200 ns

Constant

Definition at line 55 of file tb_tst_serloop2_b3.vhd.

delay_time

delay_time Delay_length := 2 ns

Constant

Definition at line 56 of file tb_tst_serloop2_b3.vhd.

sysclk

sysclk simclk

Instantiation

Definition at line 66 of file tb_tst_serloop2_b3.vhd.

gen_clksys

gen_clksys sfs_gsim_core

Instantiation

Definition at line 77 of file tb_tst_serloop2_b3.vhd.

gen_clkser

gen_clkser sfs_gsim_core

Instantiation

Definition at line 88 of file tb_tst_serloop2_b3.vhd.

uut

uut sys_tst_serloop2_b3

Instantiation

Definition at line 100 of file tb_tst_serloop2_b3.vhd.

gentb

gentb tb_tst_serloop

Instantiation

Definition at line 116 of file tb_tst_serloop2_b3.vhd.

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The documentation for this design unit was generated from the following file:

• sys_gen/tst_serloop/basys3/tb/tb_tst_serloop2_b3.vhd