w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Signals
sim Architecture Reference
Architecture >> sim

Constants

clock_period  Delay_length := 10 ns
clock_offset  Delay_length := 200 ns
delay_time  Delay_length := 2 ns

Signals

CLK100  slbit := ' 0 '
I_RXD  slbit := ' 1 '
O_TXD  slbit := ' 1 '
I_SWI  slv8 := ( others = > ' 0 ' )
I_BTN  slv5 := ( others = > ' 0 ' )
O_FUSP_RTS_N  slbit := ' 0 '
I_FUSP_CTS_N  slbit := ' 0 '
I_FUSP_RXD  slbit := ' 1 '
O_FUSP_TXD  slbit := ' 1 '
RXD  slbit := ' 1 '
TXD  slbit := ' 1 '
SWI  slv8 := ( others = > ' 0 ' )
BTN  slv5 := ( others = > ' 0 ' )
FUSP_RTS_N  slbit := ' 0 '
FUSP_CTS_N  slbit := ' 0 '
FUSP_RXD  slbit := ' 1 '
FUSP_TXD  slbit := ' 1 '

Instantiations

sysclk  simclk <Entity simclk>
uut  sys_tst_serloop1_n3 <Entity sys_tst_serloop1_n3>
gentb  tb_tst_serloop <Entity tb_tst_serloop>

Detailed Description

Definition at line 36 of file tb_tst_serloop1_n3.vhd.

Member Data Documentation

◆ CLK100

CLK100 slbit := ' 0 '
Signal

Definition at line 38 of file tb_tst_serloop1_n3.vhd.

◆ I_RXD

I_RXD slbit := ' 1 '
Signal

Definition at line 40 of file tb_tst_serloop1_n3.vhd.

◆ O_TXD

O_TXD slbit := ' 1 '
Signal

Definition at line 41 of file tb_tst_serloop1_n3.vhd.

◆ I_SWI

I_SWI slv8 := ( others = > ' 0 ' )
Signal

Definition at line 42 of file tb_tst_serloop1_n3.vhd.

◆ I_BTN

I_BTN slv5 := ( others = > ' 0 ' )
Signal

Definition at line 43 of file tb_tst_serloop1_n3.vhd.

◆ O_FUSP_RTS_N

O_FUSP_RTS_N slbit := ' 0 '
Signal

Definition at line 45 of file tb_tst_serloop1_n3.vhd.

◆ I_FUSP_CTS_N

I_FUSP_CTS_N slbit := ' 0 '
Signal

Definition at line 46 of file tb_tst_serloop1_n3.vhd.

◆ I_FUSP_RXD

I_FUSP_RXD slbit := ' 1 '
Signal

Definition at line 47 of file tb_tst_serloop1_n3.vhd.

◆ O_FUSP_TXD

O_FUSP_TXD slbit := ' 1 '
Signal

Definition at line 48 of file tb_tst_serloop1_n3.vhd.

◆ RXD

RXD slbit := ' 1 '
Signal

Definition at line 50 of file tb_tst_serloop1_n3.vhd.

◆ TXD

TXD slbit := ' 1 '
Signal

Definition at line 51 of file tb_tst_serloop1_n3.vhd.

◆ SWI

SWI slv8 := ( others = > ' 0 ' )
Signal

Definition at line 52 of file tb_tst_serloop1_n3.vhd.

◆ BTN

BTN slv5 := ( others = > ' 0 ' )
Signal

Definition at line 53 of file tb_tst_serloop1_n3.vhd.

◆ FUSP_RTS_N

FUSP_RTS_N slbit := ' 0 '
Signal

Definition at line 55 of file tb_tst_serloop1_n3.vhd.

◆ FUSP_CTS_N

FUSP_CTS_N slbit := ' 0 '
Signal

Definition at line 56 of file tb_tst_serloop1_n3.vhd.

◆ FUSP_RXD

FUSP_RXD slbit := ' 1 '
Signal

Definition at line 57 of file tb_tst_serloop1_n3.vhd.

◆ FUSP_TXD

FUSP_TXD slbit := ' 1 '
Signal

Definition at line 58 of file tb_tst_serloop1_n3.vhd.

◆ clock_period

clock_period Delay_length := 10 ns
Constant

Definition at line 60 of file tb_tst_serloop1_n3.vhd.

◆ clock_offset

clock_offset Delay_length := 200 ns
Constant

Definition at line 61 of file tb_tst_serloop1_n3.vhd.

◆ delay_time

delay_time Delay_length := 2 ns
Constant

Definition at line 62 of file tb_tst_serloop1_n3.vhd.

◆ sysclk

sysclk simclk
Instantiation

Definition at line 72 of file tb_tst_serloop1_n3.vhd.

◆ uut

uut sys_tst_serloop1_n3
Instantiation

Definition at line 100 of file tb_tst_serloop1_n3.vhd.

◆ gentb

gentb tb_tst_serloop
Instantiation

Definition at line 116 of file tb_tst_serloop1_n3.vhd.

The documentation for this design unit was generated from the following file: