w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_stim 

Constants

pcb_delay  Delay_length := 1 ns

Signals

MM_CE_N  slbit := ' 1 '
MM_OE_N  slbit := ' 1 '
MM_WE_N  slbit := ' 1 '
MM_UB_N  slbit := ' 1 '
MM_LB_N  slbit := ' 1 '
MM_CRE  slbit := ' 0 '
MM_MWAIT  slbit := ' 0 '
MM_ADDR  slv23 := ( others = > ' 0 ' )
MM_DATA  slv16 := ( others = > ' Z ' )
TB_CE_N  slbit := ' 1 '
TB_OE_N  slbit := ' 1 '
TB_WE_N  slbit := ' 1 '
TB_UB_N  slbit := ' 1 '
TB_LB_N  slbit := ' 1 '
TB_CRE  slbit := ' 0 '
TB_MWAIT  slbit := ' 0 '
TB_ADDR  slv23 := ( others = > ' 0 ' )
TB_DATA  slv16 := ( others = > ' Z ' )

Instantiations

uut  mt45w8mw16b <Entity mt45w8mw16b>
busdly  simbididly <Entity simbididly>

Detailed Description

Definition at line 38 of file tb_mt45w8mw16b.vhd.

Member Function/Procedure/Process Documentation

◆ proc_stim()

proc_stim

Definition at line 96 of file tb_mt45w8mw16b.vhd.

Member Data Documentation

◆ pcb_delay

pcb_delay Delay_length := 1 ns
Constant

Definition at line 40 of file tb_mt45w8mw16b.vhd.

◆ MM_CE_N

MM_CE_N slbit := ' 1 '
Signal

Definition at line 42 of file tb_mt45w8mw16b.vhd.

◆ MM_OE_N

MM_OE_N slbit := ' 1 '
Signal

Definition at line 43 of file tb_mt45w8mw16b.vhd.

◆ MM_WE_N

MM_WE_N slbit := ' 1 '
Signal

Definition at line 44 of file tb_mt45w8mw16b.vhd.

◆ MM_UB_N

MM_UB_N slbit := ' 1 '
Signal

Definition at line 45 of file tb_mt45w8mw16b.vhd.

◆ MM_LB_N

MM_LB_N slbit := ' 1 '
Signal

Definition at line 46 of file tb_mt45w8mw16b.vhd.

◆ MM_CRE

MM_CRE slbit := ' 0 '
Signal

Definition at line 47 of file tb_mt45w8mw16b.vhd.

◆ MM_MWAIT

MM_MWAIT slbit := ' 0 '
Signal

Definition at line 48 of file tb_mt45w8mw16b.vhd.

◆ MM_ADDR

MM_ADDR slv23 := ( others = > ' 0 ' )
Signal

Definition at line 49 of file tb_mt45w8mw16b.vhd.

◆ MM_DATA

MM_DATA slv16 := ( others = > ' Z ' )
Signal

Definition at line 50 of file tb_mt45w8mw16b.vhd.

◆ TB_CE_N

TB_CE_N slbit := ' 1 '
Signal

Definition at line 52 of file tb_mt45w8mw16b.vhd.

◆ TB_OE_N

TB_OE_N slbit := ' 1 '
Signal

Definition at line 53 of file tb_mt45w8mw16b.vhd.

◆ TB_WE_N

TB_WE_N slbit := ' 1 '
Signal

Definition at line 54 of file tb_mt45w8mw16b.vhd.

◆ TB_UB_N

TB_UB_N slbit := ' 1 '
Signal

Definition at line 55 of file tb_mt45w8mw16b.vhd.

◆ TB_LB_N

TB_LB_N slbit := ' 1 '
Signal

Definition at line 56 of file tb_mt45w8mw16b.vhd.

◆ TB_CRE

TB_CRE slbit := ' 0 '
Signal

Definition at line 57 of file tb_mt45w8mw16b.vhd.

◆ TB_MWAIT

TB_MWAIT slbit := ' 0 '
Signal

Definition at line 58 of file tb_mt45w8mw16b.vhd.

◆ TB_ADDR

TB_ADDR slv23 := ( others = > ' 0 ' )
Signal

Definition at line 59 of file tb_mt45w8mw16b.vhd.

◆ TB_DATA

TB_DATA slv16 := ( others = > ' Z ' )
Signal

Definition at line 60 of file tb_mt45w8mw16b.vhd.

◆ uut

uut mt45w8mw16b
Instantiation

Definition at line 77 of file tb_mt45w8mw16b.vhd.

◆ busdly

busdly simbididly
Instantiation

Definition at line 94 of file tb_mt45w8mw16b.vhd.

The documentation for this design unit was generated from the following file: