w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Signals
syn Architecture Reference
Architecture >> syn

Constants

rbaddr_sysmon  slv16 := x " fb00 "
sysid_proj  slv16 := x " 0104 "
sysid_board  slv8 := x " 09 "
sysid_vers  slv8 := x " 00 "

Signals

CLK  slbit := ' 0 '
CE_USEC  slbit := ' 0 '
CE_MSEC  slbit := ' 0 '
CLKS  slbit := ' 0 '
CES_MSEC  slbit := ' 0 '
GBL_RESET  slbit := ' 0 '
RXD  slbit := ' 1 '
TXD  slbit := ' 0 '
CTS_N  slbit := ' 0 '
RTS_N  slbit := ' 0 '
SWI  slv16 := ( others = > ' 0 ' )
BTN  slv5 := ( others = > ' 0 ' )
LED  slv16 := ( others = > ' 0 ' )
DSP_DAT  slv32 := ( others = > ' 0 ' )
DSP_DP  slv8 := ( others = > ' 0 ' )
RB_MREQ  rb_mreq_type := rb_mreq_init
RB_SRES  rb_sres_type := rb_sres_init
RB_LAM  slv16 := ( others = > ' 0 ' )
RB_STAT  slv4 := ( others = > ' 0 ' )
SER_MONI  serport_moni_type := serport_moni_init
RB_SRES_TST  rb_sres_type := rb_sres_init
RB_SRES_HIO  rb_sres_type := rb_sres_init
RB_SRES_SYSMON  rb_sres_type := rb_sres_init
RB_SRES_USRACC  rb_sres_type := rb_sres_init
RB_LAM_TST  slbit := ' 0 '
MEM_RESET  slbit := ' 0 '
MEM_REQ  slbit := ' 0 '
MEM_WE  slbit := ' 0 '
MEM_BUSY  slbit := ' 0 '
MEM_ACK_R  slbit := ' 0 '
MEM_ACK_W  slbit := ' 0 '
MEM_ACT_R  slbit := ' 0 '
MEM_ACT_W  slbit := ' 0 '
MEM_ADDR  slv17 := ( others = > ' 0 ' )
MEM_BE  slv4 := ( others = > ' 0 ' )
MEM_DI  slv32 := ( others = > ' 0 ' )
MEM_DO  slv32 := ( others = > ' 0 ' )

Instantiations

gen_clkall  s7_cmt_1ce1ce <Entity s7_cmt_1ce1ce>
iob_rs232  bp_rs232_2line_iob <Entity bp_rs232_2line_iob>
rlink  rlink_sp2c <Entity rlink_sp2c>
tst  tst_sram <Entity tst_sram>
sramctl  c7_sram_memctl <Entity c7_sram_memctl>
hio  sn_humanio_emu_rbus <Entity sn_humanio_emu_rbus>
smrb  sysmonx_rbus_base <Entity sysmonx_rbus_base>
uarb  rbd_usracc <Entity rbd_usracc>
rb_sres_or  rb_sres_or_4 <Entity rb_sres_or_4>

Detailed Description

Definition at line 72 of file sys_tst_sram_c7.vhd.

Member Data Documentation

◆ CLK

CLK slbit := ' 0 '
Signal

Definition at line 74 of file sys_tst_sram_c7.vhd.

◆ CE_USEC

CE_USEC slbit := ' 0 '
Signal

Definition at line 76 of file sys_tst_sram_c7.vhd.

◆ CE_MSEC

CE_MSEC slbit := ' 0 '
Signal

Definition at line 77 of file sys_tst_sram_c7.vhd.

◆ CLKS

CLKS slbit := ' 0 '
Signal

Definition at line 79 of file sys_tst_sram_c7.vhd.

◆ CES_MSEC

CES_MSEC slbit := ' 0 '
Signal

Definition at line 80 of file sys_tst_sram_c7.vhd.

◆ GBL_RESET

GBL_RESET slbit := ' 0 '
Signal

Definition at line 82 of file sys_tst_sram_c7.vhd.

◆ RXD

RXD slbit := ' 1 '
Signal

Definition at line 84 of file sys_tst_sram_c7.vhd.

◆ TXD

TXD slbit := ' 0 '
Signal

Definition at line 85 of file sys_tst_sram_c7.vhd.

◆ CTS_N

CTS_N slbit := ' 0 '
Signal

Definition at line 86 of file sys_tst_sram_c7.vhd.

◆ RTS_N

RTS_N slbit := ' 0 '
Signal

Definition at line 87 of file sys_tst_sram_c7.vhd.

◆ SWI

SWI slv16 := ( others = > ' 0 ' )
Signal

Definition at line 89 of file sys_tst_sram_c7.vhd.

◆ BTN

BTN slv5 := ( others = > ' 0 ' )
Signal

Definition at line 90 of file sys_tst_sram_c7.vhd.

◆ LED

LED slv16 := ( others = > ' 0 ' )
Signal

Definition at line 91 of file sys_tst_sram_c7.vhd.

◆ DSP_DAT

DSP_DAT slv32 := ( others = > ' 0 ' )
Signal

Definition at line 92 of file sys_tst_sram_c7.vhd.

◆ DSP_DP

DSP_DP slv8 := ( others = > ' 0 ' )
Signal

Definition at line 93 of file sys_tst_sram_c7.vhd.

◆ RB_MREQ

RB_MREQ rb_mreq_type := rb_mreq_init
Signal

Definition at line 95 of file sys_tst_sram_c7.vhd.

◆ RB_SRES

RB_SRES rb_sres_type := rb_sres_init
Signal

Definition at line 96 of file sys_tst_sram_c7.vhd.

◆ RB_LAM

RB_LAM slv16 := ( others = > ' 0 ' )
Signal

Definition at line 97 of file sys_tst_sram_c7.vhd.

◆ RB_STAT

RB_STAT slv4 := ( others = > ' 0 ' )
Signal

Definition at line 98 of file sys_tst_sram_c7.vhd.

◆ SER_MONI

SER_MONI serport_moni_type := serport_moni_init
Signal

Definition at line 100 of file sys_tst_sram_c7.vhd.

◆ RB_SRES_TST

RB_SRES_TST rb_sres_type := rb_sres_init
Signal

Definition at line 102 of file sys_tst_sram_c7.vhd.

◆ RB_SRES_HIO

RB_SRES_HIO rb_sres_type := rb_sres_init
Signal

Definition at line 103 of file sys_tst_sram_c7.vhd.

◆ RB_SRES_SYSMON

RB_SRES_SYSMON rb_sres_type := rb_sres_init
Signal

Definition at line 104 of file sys_tst_sram_c7.vhd.

◆ RB_SRES_USRACC

RB_SRES_USRACC rb_sres_type := rb_sres_init
Signal

Definition at line 105 of file sys_tst_sram_c7.vhd.

◆ RB_LAM_TST

RB_LAM_TST slbit := ' 0 '
Signal

Definition at line 107 of file sys_tst_sram_c7.vhd.

◆ MEM_RESET

MEM_RESET slbit := ' 0 '
Signal

Definition at line 109 of file sys_tst_sram_c7.vhd.

◆ MEM_REQ

MEM_REQ slbit := ' 0 '
Signal

Definition at line 110 of file sys_tst_sram_c7.vhd.

◆ MEM_WE

MEM_WE slbit := ' 0 '
Signal

Definition at line 111 of file sys_tst_sram_c7.vhd.

◆ MEM_BUSY

MEM_BUSY slbit := ' 0 '
Signal

Definition at line 112 of file sys_tst_sram_c7.vhd.

◆ MEM_ACK_R

MEM_ACK_R slbit := ' 0 '
Signal

Definition at line 113 of file sys_tst_sram_c7.vhd.

◆ MEM_ACK_W

MEM_ACK_W slbit := ' 0 '
Signal

Definition at line 114 of file sys_tst_sram_c7.vhd.

◆ MEM_ACT_R

MEM_ACT_R slbit := ' 0 '
Signal

Definition at line 115 of file sys_tst_sram_c7.vhd.

◆ MEM_ACT_W

MEM_ACT_W slbit := ' 0 '
Signal

Definition at line 116 of file sys_tst_sram_c7.vhd.

◆ MEM_ADDR

MEM_ADDR slv17 := ( others = > ' 0 ' )
Signal

Definition at line 117 of file sys_tst_sram_c7.vhd.

◆ MEM_BE

MEM_BE slv4 := ( others = > ' 0 ' )
Signal

Definition at line 118 of file sys_tst_sram_c7.vhd.

◆ MEM_DI

MEM_DI slv32 := ( others = > ' 0 ' )
Signal

Definition at line 119 of file sys_tst_sram_c7.vhd.

◆ MEM_DO

MEM_DO slv32 := ( others = > ' 0 ' )
Signal

Definition at line 120 of file sys_tst_sram_c7.vhd.

◆ rbaddr_sysmon

rbaddr_sysmon slv16 := x " fb00 "
Constant

Definition at line 122 of file sys_tst_sram_c7.vhd.

◆ sysid_proj

sysid_proj slv16 := x " 0104 "
Constant

Definition at line 124 of file sys_tst_sram_c7.vhd.

◆ sysid_board

sysid_board slv8 := x " 09 "
Constant

Definition at line 125 of file sys_tst_sram_c7.vhd.

◆ sysid_vers

sysid_vers slv8 := x " 00 "
Constant

Definition at line 126 of file sys_tst_sram_c7.vhd.

◆ gen_clkall

gen_clkall s7_cmt_1ce1ce
Instantiation

Definition at line 158 of file sys_tst_sram_c7.vhd.

◆ iob_rs232

iob_rs232 bp_rs232_2line_iob
Instantiation

Definition at line 167 of file sys_tst_sram_c7.vhd.

◆ rlink

rlink rlink_sp2c
Instantiation

Definition at line 202 of file sys_tst_sram_c7.vhd.

◆ tst

tst tst_sram
Instantiation

Definition at line 231 of file sys_tst_sram_c7.vhd.

◆ sramctl

sramctl c7_sram_memctl
Instantiation

Definition at line 253 of file sys_tst_sram_c7.vhd.

◆ hio

hio sn_humanio_emu_rbus
Instantiation

Definition at line 271 of file sys_tst_sram_c7.vhd.

◆ smrb

smrb sysmonx_rbus_base
Instantiation

Definition at line 285 of file sys_tst_sram_c7.vhd.

◆ uarb

uarb rbd_usracc
Instantiation

Definition at line 292 of file sys_tst_sram_c7.vhd.

◆ rb_sres_or

rb_sres_or rb_sres_or_4
Instantiation

Definition at line 301 of file sys_tst_sram_c7.vhd.

The documentation for this design unit was generated from the following file: