sim Architecture Reference

Architecture >> sim

Processes
PROCESS_72

Constants
all_z	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' Z ' )

Types
state_type	( s_idle , s_a2b , s_b2a )

Signals
R_STATE	state_type := s_idle
R_A	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' Z ' )
R_B	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' Z ' )

Detailed Description

Definition at line 36 of file simbididly.vhd.

Member Function/Procedure/Process Documentation

PROCESS_72()

PROCESS_72 ( )

Process

Definition at line 52 of file simbididly.vhd.

Member Data Documentation

state_type

state_type ( s_idle , s_a2b , s_b2a )

Type

Definition at line 38 of file simbididly.vhd.

all_z

all_z slv ( DWIDTH - 1 downto 0 ) := ( others = > ' Z ' )

Constant

Definition at line 44 of file simbididly.vhd.

R_STATE

R_STATE state_type := s_idle

Signal

Definition at line 46 of file simbididly.vhd.

R_A

R_A slv ( DWIDTH - 1 downto 0 ) := ( others = > ' Z ' )

Signal

Definition at line 47 of file simbididly.vhd.

R_B

R_B slv ( DWIDTH - 1 downto 0 ) := ( others = > ' Z ' )

Signal

Definition at line 48 of file simbididly.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/simlib/simbididly.vhd