syn Architecture Reference

Architecture >> syn

Processes
proc_regs	( CLK )
proc_next	( R_REGS , CE_USEC )

Constants
dimones	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 1 ' )
regs_init	regs_type := ( " 001 " , dimones )

Signals
R_REGS	regs_type := regs_init
N_REGS	regs_type := regs_init

Records
regs_type
rgbena	slv3
dimcnt	slv ( DWIDTH - 1 downto 0 )

Detailed Description

Definition at line 37 of file rgbdrv_master.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs (   CLK   )

Process

Definition at line 56 of file rgbdrv_master.vhd.

proc_next()

proc_next (   R_REGS ,   CE_USEC   )

Process

Definition at line 70 of file rgbdrv_master.vhd.

Member Data Documentation

regs_type

regs_type

Record

Definition at line 39 of file rgbdrv_master.vhd.

rgbena

rgbena slv3

Record

Definition at line 40 of file rgbdrv_master.vhd.

dimcnt

dimcnt slv ( DWIDTH - 1 downto 0 )

Record

Definition at line 41 of file rgbdrv_master.vhd.

dimones

dimones slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 1 ' )

Constant

Definition at line 44 of file rgbdrv_master.vhd.

regs_init

regs_init regs_type := ( " 001 " , dimones )

Constant

Definition at line 46 of file rgbdrv_master.vhd.

R_REGS

R_REGS regs_type := regs_init

Signal

Definition at line 51 of file rgbdrv_master.vhd.

N_REGS

N_REGS regs_type := regs_init

Signal

Definition at line 52 of file rgbdrv_master.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/bpgen/rgbdrv_master.vhd