rgbdrv_master Entity Reference

Inheritance diagram for rgbdrv_master:

Entities
syn	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std
slvtypes	Package <slvtypes>

Generics
DWIDTH	positive := 8

Ports
CLK	in	slbit
RESET	in	slbit := ' 0 '
CE_USEC	in	slbit
RGBCNTL	out	slv3
DIMCNTL	out	slv ( DWIDTH - 1 downto 0 )

Detailed Description

Definition at line 25 of file rgbdrv_master.vhd.

Member Data Documentation

DWIDTH

DWIDTH positive := 8

Generic

Definition at line 27 of file rgbdrv_master.vhd.

CLK

CLK in slbit

Port

Definition at line 29 of file rgbdrv_master.vhd.

RESET

RESET in slbit := ' 0 '

Port

Definition at line 30 of file rgbdrv_master.vhd.

CE_USEC

CE_USEC in slbit

Port

Definition at line 31 of file rgbdrv_master.vhd.

RGBCNTL

RGBCNTL out slv3

Port

Definition at line 32 of file rgbdrv_master.vhd.

DIMCNTL

DIMCNTL out slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 34 of file rgbdrv_master.vhd.

ieee

ieee

Library

Definition at line 19 of file rgbdrv_master.vhd.

std_logic_1164

std_logic_1164

use clause

Definition at line 20 of file rgbdrv_master.vhd.

numeric_std

numeric_std

use clause

Definition at line 21 of file rgbdrv_master.vhd.

slvtypes

slvtypes

use clause

Definition at line 23 of file rgbdrv_master.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/bpgen/rgbdrv_master.vhd